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From: | cvs-commit at gcc dot gnu.org |
Subject: | [Bug binutils/15068] tic6x - disassembly of 16 bits opcode |
Date: | Thu, 28 Mar 2013 09:25:13 +0000 |
http://sourceware.org/bugzilla/show_bug.cgi?id=15068 --- Comment #7 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> 2013-03-28 09:25:13 UTC --- CVSROOT: /cvs/src Module name: src Changes by: address@hidden 2013-03-28 09:25:11 Modified files: include/opcode : ChangeLog tic6x-opcode-table.h gas/testsuite : ChangeLog gas/testsuite/gas/tic6x: insns16-lsd-unit.d insns16-lsd-unit.s Log message: PR binutils/15068 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. * gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add and xor. * gas/tic6x/insns16-lsd-unit.d: Update expected output. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/ChangeLog.diff?cvsroot=src&r1=1.491&r2=1.492 http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/tic6x-opcode-table.h.diff?cvsroot=src&r1=1.6&r2=1.7 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.2211&r2=1.2212 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/tic6x/insns16-lsd-unit.d.diff?cvsroot=src&r1=1.1&r2=1.2 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/tic6x/insns16-lsd-unit.s.diff?cvsroot=src&r1=1.1&r2=1.2 -- Configure bugmail: http://sourceware.org/bugzilla/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.
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