[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3

[lotharlutz at gmx dot de]

https://sourceware.org/bugzilla/show_bug.cgi?id=16017

--- Comment #5 from Markus Mayer <lotharlutz at gmx dot de> ---
As I don't know what limitations exists for PLT entries I will provide
different solutions.

Base assumptions:
- The IP register must contain the (absolute)address of the GOT entry (I think
it is needed for lazy binding)

- If any register (except the IP register) is modified during the PLT
execution, its state must be restored before the end of the PLT

- All PLT entries must have equal sizes


Solution 1:
1: b401            push    {r0}
2: f8df 0010       ldr.w   r0, [pc, #16]   ; load GOT index
3: f8df c010       ldr.w   ip, [pc, #16]   ; load (relative) GOT address
4: 4484            add     ip, r0
5: 44fc            add     ip, pc
6: bc01            pop     {r0}
7: f8dc f000       ldr.w   pc, [ip]
8: 00000000        ; GOT index
9: 00000000        ; GOT address relative to instruction in line 5

Pros: capable to handle arbitrary large GOT indexes as well as arbitrary
offsets of the GOT
Cons: 28 Bytes per entry, 3 Load Instructions

Solution 2:
1: f8df c008       ldr.w   ip, [pc, #8]    ; load (relative)GOT entry address
2: 44fc            add     ip, pc
3: f8dc f000       ldr.w   pc, [ip]
4: 0000            ; padding to make the address aligned
5: 00000000        ; (GOT + GOT index) relative to instruction in line 2

Pros: only 16 Bytes per entry
Cons: still 2 load instructions, GOT and GOT index must be combined (is this
possible?)

Solution 3:
1: f04f 0c00       mov.w   ip, #0
2: ea4f 3c0c       mov.w   ip, ip, lsl #12
3: f20f 0c00       addw    ip, pc, #0
4: f8dc f000       ldr.w   pc, [ip]

The GOT entry address is encoded in line 1 and line 3.
Pro: 16 Bytes per entry, only one load instruction
Con: only offsets up to 24 Bit are possible. (Note this limitation also exists
for the current arm PLT)

I favour solution 3. I will provide code the generate a thumb plt later the
day.

-- 
You are receiving this mail because:
You are on the CC list for the bug.