Patch for bug in mips16 disassembler

[Benet Winder]

Hello.

I've found a small bug in the mips16 disassembler.  It's in the
troublesome part which tries to decide if a PC-relative data reference
instruction lies in the delay slot of a previous jump instruction.

Code which, for example, disassembles as:

    81e837e4:   1b43 1823   jal 0x81e8608d
    81e837e8:   6500        nop
    81e837ea:   b206        lw  v0,0x81e837fc

should instead be:

    81e837e4:   1b43 1823   jal 0x81e8608d
    81e837e8:   6500        nop
    81e837ea:   b206        lw  v0,0x81e83800

I.e. it's currently mistaking the second halfword of the 32-bit jump
instruction for the first halfword of one.

Here is a patch which I'm pretty sure fixes it. It looks one more
instruction halfword back for the start of a 32-bit jump instruction.
I'm fairly certain there is no need to go back any further, because a
jump instruction is not allowed in the delay slot of another jump
instruction.

The version I've tried it in is binutils-2.27, but the code in the git
tree is the same.  I have only tried it on little-endian code.

Benet


diff opcodes/mips-dis.c.orig opcodes/mips-dis.c
1931c1931,1937
<                       & 0xf800) == 0x1800))
---
>                       & 0xf800) == 0x1800)
>                  && !(info->read_memory_func (memaddr - 6, buffer,
>                          2, info) == 0
>                      && (((info->endian == BFD_ENDIAN_BIG
>                            ? bfd_getb16 (buffer)
>                            : bfd_getl16 (buffer))
>                           & 0xf800) == 0x1800)))