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[Bug binutils/21124] [PowerPC] Source and target registers must be diffe
cvs-commit at gcc dot gnu.org
[Bug binutils/21124] [PowerPC] Source and target registers must be different for some load instructions - should be decoded as invalid
Mon, 06 Mar 2017 11:34:27 +0000
--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot
The master branch has been updated by Alan Modra <address@hidden>:
Author: Alan Modra <address@hidden>
Date: Mon Mar 6 19:39:34 2017 +1030
Don't decode powerpc insns with invalid fields
Certain insns have restrictions on fields. For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields. This holds even when the RA0
field is 0 (meaning a zero rather than r0).
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
(extract_raq, extract_ras, extract_rbx): New functions.
(powerpc_operands): Use opposite corresponding insert function.
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
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- [Bug binutils/21124] [PowerPC] Source and target registers must be different for some load instructions - should be decoded as invalid,
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