[Bug gas/24559] New: load pseudo-operation handling bug with Armv8-M Baseline

[avieira at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=24559

            Bug ID: 24559
           Summary: load pseudo-operation handling bug with Armv8-M
                    Baseline
           Product: binutils
           Version: 2.33 (HEAD)
            Status: NEW
          Severity: normal
          Priority: P2
         Component: gas
          Assignee: unassigned at sourceware dot org
          Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

Hello,

When trying to assemble a load pseudo-operation for Cortex-M23 gas currently
incorrectly errors out:

$ cat t.s
ldr r0, =(0x30)
$ arm-none-eabi-as -mcpu=cortex-m23 t.s
t.s: Assembler messages:
t.s:1: Error: cannot honor width suffix -- `ldr r0,=(0x30)'

The same works for Cortex-M0:
$ arm-none-eabi-as -mcpu=cortex-m0 t.s
$ arm-none-eabi-objdump -dr

a.out:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   4800            ldr     r0, [pc, #0]    ; (4 <.text+0x4>)
   2:   0000            .short  0x0000
   4:   00000030        .word   0x00000030


I have found the issue to lie with the inst.size_req check that is there to
make sure we do not end up with T32 instructions for Thumb-1 targets.  However,
in the case of Armv8-M Baseline the T32 MOVW instructions are allowed.  I have
a patch for this that I will be sending to the mailing list soon.

This patch will lead to the following behavior:
$ cat t.s
ldr r0, =(0x30)
$ arm-none-eabi-as -mcpu=cortex-m23 t.s
$ arm-none-eabi-objdump -dr

a.out:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   f240 0030       movw    r0, #48 ; 0x30

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