[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Bug ld/24226] Need advise on the binutils problem that generating wrong
From: |
nelsonc1225 at sourceware dot org |
Subject: |
[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend |
Date: |
Tue, 06 Sep 2022 05:55:05 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=24226
Nelson Chu <nelsonc1225 at sourceware dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |nelsonc1225 at sourceware dot
org
--- Comment #6 from Nelson Chu <nelsonc1225 at sourceware dot org> ---
(In reply to Jim Wilson from comment #4)
> There is still a linker issue here, in that the linker should generate an
> error when the reloc overflows and computes the wrong address.
Seems hard to check this in linker since the lui and lw are not chained
together.
Consider the following reduced test case,
% cat tmp.s
lui a5, %hi(g_0x2c7fc)
lw a4, %lo(g_0x2c7fc)(a5)
lui a5, %hi(g_0x2c7fc+4)
lw a4, %lo(g_0x2c7fc+4)(a5)
lui a5, %hi(g_0x2c800)
lw a4, %lo(g_0x2c800)(a5)
% riscv64-unknown-elf-as tmp.s -o tmp.o
% riscv64-unknown-elf-ld -defsym g_0x2c7fc=0x2c7fc -defsym g_0x2c800=0x2c800
tmp.o
/Users/nelsonc/work/build-upstream/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-ld:
warning: cannot find entry symbol _start; defaulting to 00000000000100b0
% riscv64-unknown-elf-objdump -d a.out
a.out: file format elf64-littleriscv
Disassembly of section .text:
00000000000100b0 <__BSS_END__-0x1018>:
100b0: 0002c7b7 lui a5,0x2c
100b4: 7fc7a703 lw a4,2044(a5) # 2c7fc <g_0x2c7fc>
100b8: 0002d7b7 lui a5,0x2d
100bc: 8007a703 lw a4,-2048(a5) # 2c800
<g_0x2c800>
100c0: 0002d7b7 lui a5,0x2d
100c4: 8007a703 lw a4,-2048(a5) # 2c800
<g_0x2c800>
We don't chain the low instruction to it's lui, so we don't even know if the
lui is missing or cannot be shared (changed from 0x2c to 0x2d). Compared to
auipc, since the low instructions are chained to quips, so we can check these
in details,
https://github.com/bminor/binutils-gdb/blob/master/bfd/elfnn-riscv.c#L1884
--
You are receiving this mail because:
You are on the CC list for the bug.
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend,
nelsonc1225 at sourceware dot org <=