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[Bug binutils/27809] RISC-V missing disassembler options in document
From: |
nelsonc1225 at sourceware dot org |
Subject: |
[Bug binutils/27809] RISC-V missing disassembler options in document |
Date: |
Tue, 06 Sep 2022 08:32:42 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=27809
Nelson Chu <nelsonc1225 at sourceware dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |FIXED
--- Comment #1 from Nelson Chu <nelsonc1225 at sourceware dot org> ---
Should be fixed in the commit 3a337a86, so marked as resolved and fixed.
https://github.com/bminor/binutils-gdb/commit/3a337a86d9d273b5da57b1cd8ecec4baa7e95e33
commit 3a337a86d9d273b5da57b1cd8ecec4baa7e95e33
Refs: gdb-11-branchpoint-1308-g3a337a86d9d
Author: Andrew Burgess <aburgess@redhat.com>
AuthorDate: Tue Sep 28 22:11:42 2021 +0100
Commit: Andrew Burgess <aburgess@redhat.com>
CommitDate: Fri Nov 26 10:18:35 2021 +0000
opcodes/riscv: add disassembler options support to libopcodes
In preparation for the next commit, which will add GDB support for
RISC-V disassembler options, this commit restructures how the
disassembler options are managed within libopcodes.
The implementation provided here is based on this mailing list patch
which was never committed:
https://sourceware.org/pipermail/binutils/2021-January/114944.html
which in turn took inspiration from the MIPS implementation of the
same feature.
The biggest changes from the original mailing list post are:
1. The GDB changes have been split into a separate patch, and
2. The `riscv_option_args_privspec` variable, which held the valid
priv-spec values is now gone, instead we use the `riscv_priv_specs`
array from bfd/cpu-riscv.c instead.
Co-authored-by: Simon Cook <simon.cook@embecosm.com>
include/ChangeLog:
* dis-asm.h (disassembler_options_riscv): Declare.
opcodes/ChangeLog:
* riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
(riscv_options): New static global.
(disassembler_options_riscv): New function.
(print_riscv_disassembler_options): Rewrite to use
disassembler_options_riscv.
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