[Bug gas/31326] New: SCFI must handle non QWORD ALU with imm and MOV ops correctly

[indu.bhagat at oracle dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=31326

            Bug ID: 31326
           Summary: SCFI must handle non QWORD ALU with imm and MOV ops
                    correctly
           Product: binutils
           Version: 2.43 (HEAD)
            Status: NEW
          Severity: normal
          Priority: P2
         Component: gas
          Assignee: unassigned at sourceware dot org
          Reporter: indu.bhagat at oracle dot com
  Target Milestone: ---

As per the x86 ISA manual:
  - 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result
in the destination general-purpose register.
  - 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56
bits or 48 bits (respectively) of the destination general-purpose register are
not modified by the operation.

Unlike previously thought, sub-QWORD ALU/imm and MOV ops _do_ have implications
on SCFI.  SCFI/ginsn machinery does not track operation size in the ginsn
representation.  But given that these sub-QWORD ops update only a portion of a
64-bit destination register, for SCFI purposes, this needs to be deemed as an
untraceable update (when the destination is REG_SP / REG_FP). Although in most
cases, sub-QWORD ops are not expected for stack management, but the SCFI
machinery must behave correctly, when such ops are indeed present.

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