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bug#54730: AW: bug#54730: 28.1; vhdl-update-sensitivity-list not working


From: Cyril Arnould
Subject: bug#54730: AW: bug#54730: 28.1; vhdl-update-sensitivity-list not working in Windows
Date: Tue, 5 Apr 2022 17:08:28 +0000

I’ve added an example file you can visit in the attachment. To reproduce, simply

put the cursor inside the process (M-g-g 30 RET) and execute

vhdl-update-sensitivity-list-process (C-c C-u C-s). I’m getting the following backtrace:

 

Debugger entered--Lisp error: (void-variable proc-end)

  (vhdl-re-search-forward "[<:]=" proc-end t)

  eval((vhdl-re-search-forward "[<:]=" proc-end t))

  vhdl-update-sensitivity-list()

  vhdl-update-sensitivity-list-process()

  funcall-interactively(vhdl-update-sensitivity-list-process)

  command-execute(vhdl-update-sensitivity-list-process)

 

Thanks!

 

Von: Eli Zaretskii
Gesendet: Dienstag, 5. April 2022 18:43
An: Cyril Arnould
Cc: 54730@debbugs.gnu.org
Betreff: Re: bug#54730: 28.1; vhdl-update-sensitivity-list not working in Windows

 

> From: Cyril Arnould <cyril.arnould@outlook.com>
> Date: Tue, 5 Apr 2022 16:17:37 +0000
>
> vhdl-update-sensitivity-list is not working anymore in Windows.

You say "on Windows" because it works on other systems?

> I have a very simple process:
>
>   -- Flip Flops
>   p_memzing : process (Clk_CI, Rst_RBI)
>   begin
>     if Rst_RBI = '0' then               -- asynchronous reset (active low)
>       BlockCount_DP <= (others => '0');
>       Length_DP     <= (others => '0');
>     elsif Clk_CI'event and Clk_CI = '1' then  -- rising clock edge
>       BlockCount_DP <= BlockCount_DN;
>       Length_DP     <= Length_DN;
>     end if;
>   end process p_memzing;
>
> If I execute vhdl-update-sensitivity-list-process, I get the error
> message "Symbol’s value as variable is void: proc-end". If I execute
> vhdl-update-sensitivity-list-buffer instead, I get no error message but
> the sensitivity list is not updated properly, e.g. if I delete Clk_CI
> from the sensitivity list, it is not added back.

Can you please provide a complete recipe, including any file(s) one
has to visit etc.?  I don't use VHDL, so I need very precise
instructions to reproduce and debug the problem.  I'm a bit surprised
that you get that void-variable error, since I see proc-end being
let-bound in vhdl-update-sensitivity-list.  I'm probably missing
something.  Could you perhaps set debug-on-error non-nil, and post the
Lisp backtrace from the error?

Thanks.

 

Attachment: counter.vhdl
Description: counter.vhdl


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