[bug #18502] Suboptimal cache configuration for IA-32 processors

[Richard Braun]

URL:
  <http://savannah.gnu.org/bugs/?18502>

                 Summary: Suboptimal cache configuration for IA-32 processors
                 Project: The GNU Hurd
            Submitted by: syn
            Submitted on: Sunday 12/10/2006 at 19:48
                Category: GNU Mach
                Severity: 3 - Normal
                Priority: 5 - Normal
              Item Group: Hardware Support
                  Status: None
                 Privacy: Public
             Assigned to: None
         Originator Name: 
        Originator Email: 
             Open/Closed: Open
         Discussion Lock: Any
         Reproducibility: Every Time
              Size (loc): None
         Planned Release: None
                  Effort: 0.00
Wiki-like text discussion box: 

    _______________________________________________________

Details:

GNU Mach operates with a low-performance caching mode. When running, Control
Register 0 (CR0) value is 0xe001001b. The CD (cache disable) and NW (Not
Write-back/through) bits are set. This doesn't completely disable cache usage
(at least on modern processors), but makes the processor use a suboptimal
mode. See IA-32 Intel Architecture Software Developer's Manual Volume 3:
System Programming Guide, 10.5.1 Cache Control Registers and Bits, Figure
10-5.




    _______________________________________________________

Reply to this item at:

  <http://savannah.gnu.org/bugs/?18502>

_______________________________________________
  Message sent via/by Savannah
  http://savannah.gnu.org/