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Re: cache coherency in DMA and MMIO

From: Da Zheng
Subject: Re: cache coherency in DMA and MMIO
Date: Sat, 24 Apr 2010 19:39:58 +0800
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On 10-4-24 下午6:37, Samuel Thibault wrote:
>>> It does (or should do): such pointers have the __io qualifier.
>> I checked the code of e1000 again. The data for MMIO is qualified by __iomem,
> Right, I hadn't checked the precise name :)
>> but the data in the transmission or receiving queues (which are accessed by 
>> DMA)
>> doesn't have __iomem or any similar qualifiers.
> Because they are only accessed by DMA, aren't they?
They are only modified by DMA but the cpu still needs to read their values.
>> I guess the data in the transmission queue is very unlikely to be in
>> registers when the driver accesses it.
> You said yourself that DMAs take care of cache coherency :)
> (and I indeed guess they do).
At first I thought you meant any variables that can be modified by a device
should have the volatile qualifier.

According to what I read, data accessed by DMA is cache coherent on the x86
architecture. However, cache coherency cannot have variables in registers
updated so we need volatile qualifier to keep these variables out of registers.
If a variable doesn't have the volatile qualifier and If it is in a register at
the moment it is modified by DMA, the value in the register is out-of-date. But
I think this case is unlikely to happen to the data in the transmission queue in

Zheng Da

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