[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

[Markus Elfring]

Follow-up Comment #3, bug #51292 (project make):

Another example by Mike Gran:

demo: $(guile (root->list-of-objects "demo"))
        $(CC) $(LDFLAGS) -o $@ $^


You showed an other interesting use case. It seems that only simple input file
dependencies would be constructed.
I guess that the concrete function parameter "demo" can also be replaced by a
corresponding variable reference.

It fits only partly to the proposed software extension which should perform
generation of make rules similar to static pattern rules.


I imagine that it will become a general software development challenge to
achieve consensus for the required parameters of such callback functions (and
the corresponding notation).

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