[Commit-gnuradio] r9581 - gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib

[ets]

Author: ets
Date: 2008-09-15 10:29:14 -0600 (Mon, 15 Sep 2008)
New Revision: 9581

Modified:
   
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
Log:
separated command and data buffers.  Resized: chan=1k->2k, cmnd=1k->256

Modified: 
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 
    2008-09-15 15:54:38 UTC (rev 9580)
+++ 
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 
    2008-09-15 16:29:14 UTC (rev 9581)
@@ -43,10 +43,10 @@
 module rx_buffer_inband 
 #(
        parameter NUM_CHAN                      = 2,
-//     parameter CMND_FIFO_SIZE        = 1024,
-//     parameter CMND_FIFO_SZ_L2       = 10,
-       parameter CHAN_FIFO_SIZE        = 1024,
-       parameter CHAN_FIFO_SZ_L2       = 10
+       parameter CMND_FIFO_SIZE        = 256,
+       parameter CMND_FIFO_SZ_L2       = 8,
+       parameter CHAN_FIFO_SIZE        = 2048,
+       parameter CHAN_FIFO_SZ_L2       = 11
 )( 
        //control       
        input rxclk,    //master clock
@@ -213,10 +213,6 @@
        wire chan_rd;
 
        //declare nets to be assigned by generate below
-       wire interleaved[NUM_CHAN:0];
-       wire i_wren[NUM_CHAN:0];
-       wire i_flush[NUM_CHAN:0];
-
        reg [6:0] num_pkt[NUM_CHAN:0];
 
        wire [63:0] i_header_data[NUM_CHAN:0];  
@@ -239,27 +235,12 @@
        wire [7:0]      dbg_sample_counter[NUM_CHAN:0];
 
        genvar i;
-       generate for (i=0; i <= NUM_CHAN; i=i+1)
+       generate for (i=1; i <= NUM_CHAN; i=i+1)
        begin : cb
 
-               //the control channel (0) is connected differently
-               //TODO: maybe this should be broken out for clarity
-               if (i == 0) begin
-                       assign interleaved[i] = 0;
-                       assign i_wren[i] = rx_WR;
-                       assign i_flush[i] = cmd_flush;
-                       assign i_header_data[i][`CB_CHAN] = 5'h1f;
-                       assign i_header_data[i][`CB_RSSI] = 6'd0;
-                       assign i_header_data[i][`CB_UNDERRUN] = 1'b0;
-               end
-               else begin
-                       assign interleaved[i] = 1;
-                       assign i_wren[i] = rxstrobe;
-                       assign i_flush[i] = 0;
-                       assign i_header_data[i][`CB_CHAN] = i-1;
-                       assign i_header_data[i][`CB_RSSI] = i_rssi[i-1];
-                       assign i_header_data[i][`CB_UNDERRUN] = 
tx_underrun[i-1];
-               end
+               assign i_header_data[i][`CB_CHAN] = i-1;
+               assign i_header_data[i][`CB_RSSI] = i_rssi[i-1];
+               assign i_header_data[i][`CB_UNDERRUN] = tx_underrun[i-1];
                                
                assign i_header_data[i][`CB_OVERRUN] = 1'b0; //generated in 
channel_buffer
                assign i_header_data[i][`CB_PAYLOAD_LEN] = 9'd0; //not 
currently an input (auto-generated)
@@ -277,9 +258,9 @@
                        .reset                  ( reset                         
                ),
                        
                        .wrclk                  ( rxclk                         
                ),
-                       .interleaved    ( interleaved[i]                        
),
-                       .wren                   ( i_wren[i]                     
                ),
-                       .flush_packet   ( i_flush[i]                            
),
+                       .interleaved    ( 1'b1                                  
        ),
+                       .wren                   ( rxstrobe                      
                ),
+                       .flush_packet   ( 1'b0                                  
        ),
                        
                        .rdclk                  ( usbclk_inv                    
        ),
                        .rd_data_en             ( chan_en[i] & chan_rd          
),
@@ -306,7 +287,57 @@
        end
        endgenerate
 
+
        
/////////////////////////////////////////////////////////////////////////
+       // Command Channel Buffer
+
+               assign i_header_data[0][`CB_CHAN] = 5'h1f;
+               assign i_header_data[0][`CB_RSSI] = 6'd0;
+               assign i_header_data[0][`CB_UNDERRUN] = 1'b0;
+
+               assign i_header_data[0][`CB_OVERRUN] = 1'b0; //generated in 
channel_buffer
+               assign i_header_data[0][`CB_PAYLOAD_LEN] = 9'd0; //not 
currently an input (auto-generated)
+               assign i_header_data[0][`CB_TIMESTAMP] = timestamp;
+               
+               assign i_header_data[0][`CB_NON_INPUTS] = 0;
+
+               rx_channel_buffer  
+               #(
+                       .CD_FIFO_SIZE   ( CMND_FIFO_SIZE        ),
+                       .CD_FIFO_SZ_L2  ( CMND_FIFO_SZ_L2       )
+               )
+               chan_buf[0]
+               (
+                       .reset                  ( reset                         
                ),
+                       
+                       .wrclk                  ( rxclk                         
                ),
+                       .interleaved    ( 1'b0                                  
                ),
+                       .wren                   ( rx_WR                         
                ),
+                       .flush_packet   ( cmd_flush                             
        ),
+                       
+                       .rdclk                  ( usbclk_inv                    
        ),
+                       .rd_data_en             ( chan_en[0] & chan_rd          
),
+                       .rd_header_en   ( chan_en[0] & header_rd        ),
+                       .num_packets    ( num_pkt[0]                            
),
+                       .packet_rdy             ( chans_ready[0]                
        ),
+                       .overrun                ( overrun[0]                    
        ),
+                       
+                       .i_chan_data_i  ( i_chan_data_i[0]                      
),
+                       .i_chan_data_q  ( i_chan_data_q[0]                      
),
+                       .i_header_data  ( i_header_data[0]                      
),
+                       .o_chan_data    ( o_chan_data[0]                        
),
+                       .o_header_data  ( o_header_data[0]                      
)
+                       
+                       //debug
+                       ,.dbg_ph_wrusedw                ( dbg_ph_wrusedw[0]     
        )
+                       ,.dbg_cd_wrusedw                ( dbg_cd_wrusedw[0]     
        )
+                       ,.dbg_ph_full                   ( dbg_ph_full[0]        
        )
+                       ,.dbg_cd_full                   ( dbg_cd_full[0]        
        )
+                       ,.dbg_save_header               ( dbg_save_header[0]    
)
+                       ,.dbg_sample_counter    ( dbg_sample_counter[0] )
+               );
+
+       
/////////////////////////////////////////////////////////////////////////
        // Channel Selector
        wire pkt_complete;