[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Discuss-gnuradio] [IP] Intel tips plans for reconfigurable radio archi

From: Eugen Leitl
Subject: [Discuss-gnuradio] [IP] Intel tips plans for reconfigurable radio architecture (fwd)
Date: Fri, 24 Jan 2003 15:58:42 +0100 (CET)

---------- Forwarded message ----------
Date: Fri, 24 Jan 2003 09:16:03 -0500
From: Dave Farber <address@hidden>
To: ip <address@hidden>
Subject: [IP] Intel tips plans for reconfigurable radio architecture

------ Forwarded Message
From: Dewayne Hendricks <address@hidden>

Intel tips plans for reconfigurable radio architecture
By Ron Wilson, EE Times
Jan 22, 2003 (11:16 AM)
URL: <http://www.commsdesign.com/story/OEG20030122S0037>

SAN JOSE, Calif. - Intel Corp. provided the first details of its
reconfigurable radio architecture this week at the Software-Defined
Radio Forum, where the company described an array of processors that
will implement a range of physical layer and media-access control

In its first public discussion of its plans since Intel's chief
technology officer Patrick Gelsinger revealed an intent to pursue
reconfigurable radio at last year's Intel Developer Forum, Intel made
it clear that its approach will differ from most other companies at
the workshop. Rather than relying on programmable logic, Intel
researcher Jeffrey Schiffer said Monday (Jan. 20) that the company's
architecture will use a heterogeneous array of processors. Some will
be general-purpose DSPs, and others will be tuned to process
particular algorithms. Schiffer said the individual processors will
be of intermediate complexity, between an FPGA and a modest CPU.

The processors are not bused, but rather are connected through a mesh
that emphasizes nearest-neighbor relationships. This both offers a
natural implementation for data flow organizations and reduces the
power and signal integrity issues that come with long interconnect

The mesh of processors is terminated on two sides by an array of I/O
engines, with one array serving as an input device and the other
serving as output. In front of the input processors resides a
switchable array of analog front-ends - and, presumably, antennas -
allowing the entire system to hop gracefully between frequency bands.
Different analog front-ends provide different pre-filtering and
signal capture/conversion. Behind the output array lives a collection
of various media-access controller (MAC) devices.

Transparent configuration

Intel conceives the architecture as a solution to the problem of
highly mobile digital appliances that must move not only from cell to
cell, but from protocol to protocol and band to band in order to
maintain connectivity. In operation, the proposed Intel device would
continually query its environment to determine what services were
available. It would then switch on the appropriate antenna and analog
front-end combination to connect to the service, and configure out of
the processor array an appropriate PHY/MAC layer implementation for
that standard. This process would be transparent to the user, except
for permission and billing issues.

Intel researchers have estimated that such a configurable array
approach would be considerably less efficient, in both real estate
and power, than a hard-wired PHY/MAC solution, or even two of them.
But when the number of PHY/MAC combinations that must be supported
reaches three, the Intel approach breaks even with dedicated engines.
Above that number, the array is more efficient.

Thus Intel suggested that reconfigurable radio devices of the future
will not challenge single-provider terminals. Rather, they would have
a major role when the terminal is mobile and must move freely between
numerous incompatible wireless network services.

Archives at: 
Weblog at: <http://weblog.warpspeed.com>

------ End of Forwarded Message

You are subscribed as address@hidden
To unsubscribe or update your address, click

Archives at: http://www.interesting-people.org/archives/interesting-people/

reply via email to

[Prev in Thread] Current Thread [Next in Thread]