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Re: [Discuss-gnuradio] 8 bit usrp samples (My first verilog code)

From: Martin Dvh
Subject: Re: [Discuss-gnuradio] 8 bit usrp samples (My first verilog code)
Date: Thu, 25 Aug 2005 03:15:07 +0200
User-agent: Debian Thunderbird 1.0.2 (X11/20050331)

I improved my previous verilog and driver code to get 8 bit samples from the 
usrp to get higher bandwidth.
I installed quartus II, compiled the firmware, uploaded it to my usrp and 
didn't break anything.
So I am quite happy.
It even seems that the new code does what I expected. Give 8 bit samples if you 
turn it on.

patches, firmware, descriptions and example at:

Here is the description:

Usrp 8 Bit samples

These patches add a new mode to the usrp fpga firmware, usrp driver and gr-usrp 
gnuradio driver..
This new mode only sends 8 bit samples over the usb bus in stead of 16.
It truncates the samples by discarding the 8 least significant bits.
That is why the new mode is called FPGA_MODE_TRUNC_TO_8BIT.

The reason for this code is to be able to get higher samplerates or more 
channels at the same time over the usb bus.
Depending on the speed of your usb card and mainbord you can get between 16 
MB/sec and 32 MB/sec over the usb bus.
Using 16 bit comples samples this means in the default 16 bit mode you can get a maximum of 1 channel: 8 Msamples/sec or 2 channels 4 Msamples/sec.
Using only 8 bit samples doubles this rate to 1 channel 16 Msamples/sec or 2 
channels 8 Msamples/sec.

This is my first verilog code so there could be bugs in there or I could have 
overlooked some consequences of the changes.

The first tests I did with the new code I did get 8 bit samples and it looked 
quite like I expected.
(Although I still miss samples at higher sample rates (lower decimation 
factors), even when just dumping to a ramdisk)

The one feature that is still missing is the ability to tell the usrp to shift 
the bits of the samples.
With only the 8 most significant bits you can only see very strong signals. 
Weak signals come out as just zero.
I hoped the pga gain setting would be enough to get the top 8 bits saturated 
but this is not the case.

It should be possible to implement a function in the firmware and a parameter in the driver which shifts the bits of the samples to the left but keep the sign bit.
This would be an extra a kind of gain setting with 6 dB steps.
Then you can increase this shift value untill your signal gets 

I only implemented the 8 bit feature in the receive path.

You can try the code with the new usrp_oscope_c.py example I included.
It has an option --bitdepth which takes 8 or 16 as a value (default is 16)

The patches,example and firmware can be downloaded from:

These patches alter the fpga sourcecode. You need the Quartus II web software 
from altera to build the firmware yourself.
I already build one for you, it is called usrp_fpga_8bit_3.rbf
You have to rename it to usrp_fpga.rbf and copy it to $PREFIX/share/usrp/rev2 
to use it.
(Be sure to backup your original firmware.)

I am quite happy I did not burnup my usrp when I built and uploaded this 
homebrew firmware.
But don't sew me when something breaks if you use this.

          Martin Dudok van Heel

2005-08-25  Martin Dudok van Heel  <nldudok1 at olifantasia.com>

        * firmware/include/fpga_regs_common.h,
          fpga/sdr_lib/rx_buffer.v, fpga/toplevel/usrp_std/usrp_std.v,
          host/apps/test_usrp_standard_rx.cc, host/lib/usrp_standard.cc,
          host/lib/usrp_standard.h: added 8bit samples support
          (enable by using the new mode FPGA_MODE_TRUNC_TO_8BIT)

2005-08-25  Martin Dudok van Heel  <nldudok1 at olifantasia.com>

        * src/usrp.py, src/usrp1.i, src/usrp1_source_base.cc,
          src/usrp1_source_base.h, src/usrp1_source_c.cc,
          src/usrp1_source_s.cc: added 8bit samples support
          (enable by using the new mode usrp.FPGA_MODE_TRUNC_TO_8BIT)

Martin Dvh wrote:
I wanted to be able to get 8 bit samples from the usrp so I tried to hack this into the verilog code.

Since I don't want to fry my board I didn't compile and try to install it but first want to ask if I am on the right track. (I didn't even install Quartus II web-edition yet since I am working on linux right now and I could only download a windows version. Is there a linux version?)

What I tried to do is using a bit of the FR_MODE register to set the usrp in trunc_to_8bit mode.
In that mode it puts the high 8 bits of two channels into one output word.
I don't know if the timing should also be changed somewhere.

Please have a look at it.
(it is a diff against current cvs of the usrp code)



? bootstrap-mdvh-debian
? usrp-build
? fpga/fpga_8bit.diff
Index: firmware/include/fpga_regs_common.h
RCS file: /cvsroot/opensdr/usrp/firmware/include/fpga_regs_common.h,v
retrieving revision 1.5
diff -u -b -B -r1.5 fpga_regs_common.h
--- firmware/include/fpga_regs_common.h 20 Jul 2005 16:46:07 -0000      1.5
+++ firmware/include/fpga_regs_common.h 17 Aug 2005 23:27:05 -0000
@@ -66,6 +66,7 @@
 #  define  bmFR_MODE_NORMAL                  0
 #  define  bmFR_MODE_LOOPBACK          (1 << 0)  // enable digital loopback
 #  define  bmFR_MODE_RX_COUNTING       (1 << 1)  // Rx is counting
+#  define  bmFR_MODE_TRUNC_TO_8BIT     (1 << 2)  // Rx is truncated to most 
significant 8 bits
// If the corresponding bit is set, internal FPGA debug circuitry
Index: fpga/sdr_lib/rx_buffer.v
RCS file: /cvsroot/opensdr/usrp/fpga/sdr_lib/rx_buffer.v,v
retrieving revision 1.19
diff -u -b -B -r1.19 rx_buffer.v
--- fpga/sdr_lib/rx_buffer.v    14 Aug 2004 22:33:36 -0000      1.19
+++ fpga/sdr_lib/rx_buffer.v    17 Aug 2005 23:27:05 -0000
@@ -43,6 +43,7 @@
     input rxclk,
     input rxstrobe,
     input clear_status,
+    input trunc_to_8bit,
     output [15:0] debugbus
@@ -78,12 +79,36 @@
        store_next <= #1 4'd0;
      else if(rxstrobe & (store_next == 0))
        store_next <= #1 4'd1;
-     else if(~rx_full & (store_next == channels))
+     else if(~rx_full & (store_next == channels)) //This works only for the 8 
bit case if the number of channels is even
        store_next <= #1 4'd0;
      else if(~rx_full & (store_next != 0))
+       if(trunc_to_8bit)
+         store_next <= #1 store_next + 4'd2;
+       else
        store_next <= #1 store_next + 4'd1;
always @*
+     if(trunc_to_8bit)
+       case(store_next)
+         4'd1 : begin
+                  fifodata[7:0] = ch_0[15:11];
+                  fifodata[15:11] = ch_1[15:11];
+ end + 4'd3 : begin
+                  fifodata[7:0] = ch_2[15:11];
+                  fifodata[15:11] = ch_3[15:11];
+                end
+         4'd5 : begin
+                  fifodata[7:0] = ch_4[15:11];
+                  fifodata[15:11] = ch_5[15:11];
+                end
+         4'd7 : begin
+                  fifodata[7:0] = ch_6[15:11];
+                  fifodata[15:11] = ch_7[15:11];
+                end
+         default : fifodata = 16'hFFFF;
+ endcase // case(store_next) + else //if(trunc_to_8bit)
        4'd1 : fifodata = ch_0;
        4'd2 : fifodata = ch_1;
Index: fpga/toplevel/usrp_std/usrp_std.v
RCS file: /cvsroot/opensdr/usrp/fpga/toplevel/usrp_std/usrp_std.v,v
retrieving revision 1.14
diff -u -b -B -r1.14 usrp_std.v
--- fpga/toplevel/usrp_std/usrp_std.v   20 Jul 2005 21:41:40 -0000      1.14
+++ fpga/toplevel/usrp_std/usrp_std.v   17 Aug 2005 23:27:05 -0000
@@ -197,6 +197,7 @@
wire loopback = settings[0];
    wire counter = settings[1];
+   wire trunc_to_8bit = settings[2];
always @(posedge clk64)
@@ -241,6 +242,7 @@
+       .trunc_to_8bit(trunc_to_8bit),
        .debugbus(rx_debugbus) );
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
Index: host/lib/usrp_standard.h
RCS file: /cvsroot/opensdr/usrp/host/lib/usrp_standard.h,v
retrieving revision 1.14
diff -u -b -B -r1.14 usrp_standard.h
--- host/lib/usrp_standard.h    20 Jul 2005 05:34:26 -0000      1.14
+++ host/lib/usrp_standard.h    17 Aug 2005 23:27:06 -0000
@@ -57,7 +57,8 @@
   enum {
     FPGA_MODE_NORMAL     = 0x00,
     FPGA_MODE_LOOPBACK   = 0x01,
-    FPGA_MODE_COUNTING   = 0x02
+    FPGA_MODE_COUNTING   = 0x02,
+    FPGA_MODE_TRUNC_TO_8BIT   = 0x04
~usrp_standard_rx ();


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