the memory allocated for each of the fifo in tx_buffer and rx_buffer is twice their capacity.....i.e 65K 'bits'(8192 bytes)..as seen from the compilation report of Quartus.....any specific reason?
also, when i have two Rx..Then how exactly is the rx_buffer used to store and keep seperated the data comming from 2 RX paths?
Things which could be controlled from Python on FPGA and AD/DA converters are:
Gains. Decimation Rate. Can bits/sample of AD/DA converters be controlled from Python? What else is controllable from Python?
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[Discuss-gnuradio] few more queries on FPGA,