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Re: [Discuss-gnuradio] grGPS Preliminary Schematic

From: Darrell Harmon
Subject: Re: [Discuss-gnuradio] grGPS Preliminary Schematic
Date: Thu, 6 Apr 2006 13:15:03 -0400
User-agent: Mutt/1.5.9i

On Thu, Apr 06, 2006 at 06:55:57PM +0200, Martin Dvh wrote:
> (Life would be so much easier if all the clocks on the usrp would first go 
> through the fpga.
> Which could then upconvert/divide/pll/override/combine any clock in verilog 
> software.)
> Greetings,
> Martin

The phase noise would be increased by running the clocks through the FPGA.
There is too much noise in there for an ADC clock. The FPGA PLLs are especially 
bad. The phase noise can be seen on a scope in some cases. I believe it is
somewhere around 100 ps RMS. The crystal oscillator should be around 0.5 ps
RMS. The programmable oscillators are not quite as bad as a FPGA pll, but are
close. Generally, the wideband VCOs integrated into ICs are horrible. Nothing
beats a crystal oscillator.

One interesting option for future boards is the AD9511 clock distribution IC.
It has 2 LVPECL inputs, an integrated PLL and several programmable outputs.
I am using it with a 125 MHz VCXO in a design that I am working on now. I am 
clocking DACs with the 125 MHz directly and the ADCs with 62.5 MHz which is
divided from the 125 MHz by the AD9511. I may connect the second input to the
AD9511 to a SMA jack and allow the clock to be selected in software. The only
downside to my clock scheme is is the high cost. This is going into a board 
that I am working on now which will be released in a few months (or years if
things keep going as they have been for the last few weeks).

Darrell Harmon

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