Re: [Discuss-GnuRadio]: tx_chain.v module in usrp_std.v

[Oussama Sekkat]

Hi,
Thanks for your reply.
So from what I understand, in the transmit side the digital up
converters are implemented in the AD9862 chip but the interpolation is
done in the FPGA. I believe in the receive side the down conversion is done in the FPGA. So  why can't we do the same for the transmit side and implement the Digital Up Converters in the FPGA? 
Also, the AD9862 chip contains interpolation filters as well. Could those be used instead of the CIC interpolators on the FPGA? that way both the up conversion and the interpolation would be done in the AD9862 chip and more space would be available on the FPGA.

Oussama.

On 7/11/06, Eric Blossom <address@hidden> wrote:

On Mon, Jul 10, 2006 at 08:22:29PM -0700, Oussama Sekkat wrote:
> Hello everybody,
>
> I am still a beginner in the project so bare with me if my questions have
> obvious answers.
> I was looking at the verilog code for usrp_std.v module. that module
> containes the tx_chain.v module which uses a module called
phase_acc.

Actually, if you look at that line, you'll see that it's within an
`ifdef that's not enabled.  Take a look again ;)

> I am not sure what this later module does? It takes as inputs (among others) a
> 7bit serial address and 32 bit serial data and outputs the 32bit phase.
> Does anyone have any idea what that module does and what its purpose is in
> the tx_chain?

If enabled, this code would implement digital upconversion in the
FPGA, instead of using the DUC in the AD9862.  N.B., this code hasn't
been tested in something like a couple of years and may have suffered
bit rot.  [Definitely.  The FPGA register definitions that would have
been required to use it have been removed...]

Eric