|Subject:||Re: [Discuss-GnuRadio]: tx_chain.v module in usrp_std.v|
|Date:||Wed, 12 Jul 2006 21:44:05 -0700|
Oussama Sekkat wrote:
> Thanks for your reply.
> So from what I understand, in the transmit side the digital up
> converters are implemented in the AD9862 chip but the interpolation is
> done in the FPGA.
On the transmit side we use our own CIC to interpolate from whatever
ratio comes over the USB to 32 MS/s. This is sent to the 9862 which
then interpolates again by a factor of four to bring us to 128 MS/s.
The upconverter is in the 9862 as you say.
> I believe in the receive side the down conversion is done in the FPGA.
Yes, because the 9862 does not have a downconverter in the RX path.
> So why can't we do the same for the transmit side and implement the
> Digital Up Converters in the FPGA?
Not sure what you would gain from this -- You would use a lot more area
in the FPGA.
Anyway, the bus going to the TX path on the 9862 is multiplexed (I then
Q samples), and we run it at our normal clock rate of 64 MHz. This
means we can only get 32 MS/s complex across it. If we did the
upconversion in the FPGA, we would thus be limited to about a 12 MHz
> Also, the AD9862 chip contains interpolation filters as well. Could
> those be used instead of the CIC interpolators on the FPGA? that way
> both the up conversion and the interpolation would be done in the
> AD9862 chip and more space would be available on the FPGA.
We use those interpolation filters already, but they only do a factor of
4, so we still need a CIC in the FPGA.
> On 7/11/06, *Eric Blossom* < address@hidden <mailto:address@hidden>> wrote:
> On Mon, Jul 10, 2006 at 08:22:29PM -0700, Oussama Sekkat wrote:
> > Hello everybody,
> > I am still a beginner in the project so bare with me if my
> questions have
> > obvious answers.
> > I was looking at the verilog code for usrp_std.v module. that
> > containes the tx_chain.v module which uses a module called
> Actually, if you look at that line, you'll see that it's within an
> `ifdef that's not enabled. Take a look again ;)
> > I am not sure what this later module does? It takes as inputs
> (among others) a
> > 7bit serial address and 32 bit serial data and outputs the 32bit
> > Does anyone have any idea what that module does and what its
> purpose is in
> > the tx_chain?
> If enabled, this code would implement digital upconversion in the
> FPGA, instead of using the DUC in the AD9862. N.B., this code hasn't
> been tested in something like a couple of years and may have suffered
> bit rot. [Definitely. The FPGA register definitions that would have
> been required to use it have been removed...]
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