Re: [Discuss-gnuradio] The coming deluge of CPU cycles

[Daniel O'Connor]

On Thursday 27 July 2006 15:39, Jason Hecker wrote:
> Would an extra bit of hardware such as a PCI card with PLX's PCI9030
> breaking out to the USRP with something like an 80 wire IDE cable be
> suitable for high bandwidth, low latency and lowish cost?
>
> (http://www.plxtech.com/products/io_accelerators/PCI9030/default.htm)

A 9030 is target only, you'd need a 9054, 9056, 9060 or 9080 otherwise the 
performance would not be very great.

Another option is to use a PCI soft core but then you run into licensing 
issues.

I have looked at these for work and one problem (for us anyway) is that the 
S/G engine doesn't treat the data as precious so it's not very useful for 
reading from a FIFO. It's quite frustrating because that means you have a 
chip which has an S/G engine built in but you have to make your own anyway :(

I'd love to be shown to be wrong though ;)

> I know someone who used gigabit ethernet driver chips hooked to an FPGA
>   in order to push lots of digitised SVGA video data down a long length
> of CAT5e for a KVM application.

Was that really ethernet framing? Or just using the CAT5 cable as 4 
differential pairs?
(Not that there's anything wrong with that - I imagine you'd still get good 
cable lengths with the right drivers)

-- 
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
  -- Andrew Tanenbaum
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