Hi I am looking at the usrp_std.v module and the schematics for the FPGA and the FX2/FPGA interface. It seems to me that the data of course arrives as a serial input to the FX2 chip. Then, it gets to the FPGA as a 16bit parallel input from the GPIF bus. That input is called usb_data in the FPGA. However, upon reading the verilog code of the serial_io.v module, it seems that this module does a serial to parallel conversion of the SDI input and puts it into the 32 bit serial_data output register. I am confused as to whether the serial data from the USB is converted to parallel in the FX2 chip or whether the data sent to the FPGA is serial but a verilog module inside the FPGA converts it to parallel. So I am not sure whether the data coming from the USB to the usrp_std.v module is the 16bit input usb_data or the SDI input.