Lin Ji,
here is a brief descripition of the functionality of the FPGA:
On the transmit side, the data comes as a 16 bit value from the USB. It goes through the TX buffer module. This module demuxes the data to be transmitted and decouples it into I and Q signals. Then, each complex pair of signals I, Q, goes through the TX chain module which interpolates the data to 32 MS/s. Those I, Q signals are then interleaved and sent to the AD 9862 chip where the signals are interpolated by a factor of 4, then up converted to an intermediate frequency and finally converted to an analog signal.
the receive path: The signals from the daughter boards are first converted to a 12 bit digital value in the AD 9862 chip, and decimated in the same chip. The signals then enter the ADC interface module which routes them to the proper digital down converter. Then the RX chain module in the FPGA takes care of the digital down conversion to baseband and decimation to 32MS/s. And finally, the signals go through the RX buffer module where they get interleaved into a 16 bit value. That value is the sent to the PC through the USB bus.
THe modules I mentionned above are the verilog modules that come with the GR package. You can find them in the gr-build/usrp/fpga folder.You can take a look at the verilog codes for those modules.
I hope that helps,
Oussama.
PS: I am working on a write up that describes the functionality of the FPGA and also includes a brief guide on how to edit, recompile the verilog code and program the board using Quartus II from altera. I will let the mailing list know when I'm done with the document in case anybody wants to look at it.
On 10/5/06, Lin Huang <address@hidden
> wrote:
I don't think now there is available GNU radio modules for WLAN tranceiver. The FPGA is used as DDC/DUC.
Maybe you can directly save the signal into files and then do the correlation or other processing.
Alin
2006/10/5, Lin Ji <address@hidden>:
Hi,
I'm working with analyzing WLAN signals and plan to use the onboard FPGA to process the signal.
I wonder what does this FPGA do by default? Is there any documents about this?
What I need to do is before saving the I&Q signal samples to files, do a correlation and time stamping on the incoming samples. Is this possible to do by the FPGA? I mean, can I feed the realtime stream to FPGA and process it? And if so, how? Is there some python functions which do this?
I would be very grateful if I can get some help.
/Lin
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