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Re: [Discuss-gnuradio] usrp.source_s and usrp.source_c

From: Oussama Sekkat
Subject: Re: [Discuss-gnuradio] usrp.source_s and usrp.source_c
Date: Sat, 4 Nov 2006 17:10:14 -0800

Hi Dawei,
If you want to start working on the FPGA code, you might want to start with the top level verilog modue located at gr-build/usrp/fpga/toplevel/usrp_std.v .
I don't know what kind of modification to the code you'd like to do but in any case you'll need the Altera Quartus II software.
Attached to this email you'll find a description of the functionality of the FPGA with block diagrams of the different modules. Toward the end of the document, there is a brief tutorial on how to change the verilog code and reprogram the board. (there is actually a slightly easier way to do that, but I did it the way I did because it saves a little bit of Hard drive space : about 20M.the easier way is to copy the whole usrp file)
There are still some minor details that I will add to that document later on.
I hope this document will be helpful.
Let me know if you have any questions.


On 11/4/06, Dawei Shen <address@hidden> wrote:
Thank you guys for your replies. Confusion has been cleared now.

It might have been answered for many many times, but I just wish to obtain a quick answer. Recently I have been considering moving some of my work to FPGA, where is the best place I should start with? (such as the verilog code...)


On 11/4/06, Oussama Sekkat < address@hidden> wrote:

On 11/3/06, Eric Blossom <address@hidden > wrote:
On Fri, Nov 03, 2006 at 06:58:41PM -0500, Dawei Shen wrote:
> Hi, Guys
> I am suddenly a little bit confused about the difference between
> usrp.source_s and usrp.source_c. Basically I have two questions:
> 1. Since the ADC only has 12 bits, does it mean the short integers entering
> the computer have their last four bits as zeros? Or are their first four
> digits are zero (the first bit should be the sign)?

The short integers entering the computer have been through the DDC and
have been processed as 16-bit ints.  Without looking at the verilog
code I don't recall how they're adjusted before being clocked into the

The 12 bit output form the ADC goes first through the adc_interface.v module (check the verilog code if you'd like). Inside that module, the most significant bit is propagated once to the left and 3 zero bits are shifted in from the right. The result is a 16 bit value. That value then goes through the rx_dcoffset.v module (I don't know what that does) before going to the DDCs in the rx_chain.v module.
I hope that helps.


> 2. Is anything interesting done when the short integers converted to float
> values? Or are they simply converted to a different type without changing
> the values?

At this point nothing besides the format conversion is done.

There have been some conversations about changing the _c format to be
normalized to +/- 1.0 but the details aren't worked out yet.   We'll
probably define a new interface so that we don't break a bunch of
code.  The normalization would also be a function of the kind of
daughterboard that's connected, and will probably factor in some kind
of two-tone IMD performance result.


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