[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Discuss-gnuradio] USRP and USB full speed (1.1) transmit

From: Eric Blossom
Subject: Re: [Discuss-gnuradio] USRP and USB full speed (1.1) transmit
Date: Thu, 7 Dec 2006 13:41:20 -0800
User-agent: Mutt/1.5.9i

On Thu, Dec 07, 2006 at 08:48:54AM -0500, Philip Balister wrote:
> I've been working on adding USB1.1 (full speed) support to the USRP
> software/firmware so I can use it with a TI OSK board. I've been going
> back and forth with Matt on some issues and we are getting out of his
> area of expertise. Here is summary of progress to date.
> After modifying the 8051 code I had the following behavior:
> When I compile the code for the OSK, I see two symbols transmitted,
> then dead air. Two symbols is 64 bytes (2 symbols x 8 sample/symbol x
> 4 bytes/sample), then there are 512 - 64 bytes of no signal. It feels
> like the 64 byte packets are read into a buffer of 512 bytes, where
> all the un-written bytes are zeros.

> It feels like somewhere in the USB chain, I send the 64 byte packet,
> then something reads the 64 bytes and zero pads the packet to 512
> bytes. I suspect the FPGA tries to read 512 bytes from the FX2 chip,
> but that is only because this is the area of the code I least
> understand :)

Unless your FX2 code sets up the transfer size to 64, then this is
probably what is happening.  That is, the host is sending 64 bytes,
but the FX2 is ignoring the real length, and is assuming that it's 512

Or see below, about the GPIF DMA program still tranfering 256 16-bit values.

> Matt suggested the following FPGA change, and I also chnaged a similar
> construct a few lines further on:
> http://gnuradio.utah.edu/trac/browser/gnuradio/trunk/usrp/fpga/sdr_lib/tx_buffer.v
> And look at line 94, you will see the test for "end of packet".
> write_count[8] goes high when we have put 256 elements (512 bytes) into
> the fifo.  You would need to modify this to write_count[5] which will go
> high when 32 elements (64 bytes) have been put into the fifo.
> This results in:
> Well, it looks like data is coming out, but it looks like I get 64
> bytes out, then there is a "hiccup" about 5 microseconds long. I am
> getting suspicious the OSK doesn't get the data on the USB bus fast
> enough. I'm still not entirely clear how the FX2 works. I am wondering
> if there is a way to let the buffers in the FX2 chip fill up more
> before the FPGA starts pulling data from the FX2.

Remember that the GPIF is currently set up to DMA 256 16-bit values.
Perhaps that part needs changing.  The magic value is probably buried
in the WaveData table in usrp_gpif.c

Another thing you could try is to set up the GPIF in a non-flowstate
mode.  You'd need to use the Cypress tool to do this (or Larry
Doolittle's perl (?) code.  Running in full speed, you don't need to
be able to burst data at 96MB/sec between the FX2 and FPGA.

Philip, do you have access to a logic analyzer?
It would extremely helpful for determining what's really happening
between the FX2 and FPGA.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]