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Re: [Discuss-gnuradio] AD9862 Functionality


From: Eric Blossom
Subject: Re: [Discuss-gnuradio] AD9862 Functionality
Date: Tue, 20 Feb 2007 13:37:43 -0800
User-agent: Mutt/1.5.9i

On Tue, Feb 20, 2007 at 03:50:21PM -0500, Brian Padalino wrote:
> So to just figure out the different decimations/interpolation rates we have:
> 
> ADC samples at 64MHz, and passes through both I and Q channels over
> the 24-bit RX bus.  Internal to the FPGA, the CIC automatically
> decimates by a value of at least 4.  The halfband decimating FIR
> internal to the FPGA decimates by a fixed value of 2.

Yes.  Note that some FPGA builds don't contain the half-band.

> This gives a minimum decimation rate of 8, leaving 8Msps going over
> the USB of the USRP.  Is this correct?

Yes.  
With 16-bit I & Q decim =  8 ->  8MS/sec -> 32MB/sec.
With  8-bit I & Q decim =  4 -> 16MS/sec -> 32MB/sec


> The data being clocked out of the USRP is at 64Msps.

More precisely, there are two interleaved channels, each running at
32MS/s. The AD9862 interpolates each stream by 4, giving two streams
at 128MS/s.

> There are two points that interpolation can happen - inside the
> AD9862 and internal to the FPGA.  Within the FPGA, the CIC filter is
> the interpolating structure and has a variable rate, whereas the
> AD9862 has a fixed interpolation rate of 2x if a real-only signal is
> being used, or 4x is possible if interleaved with I/Q at 64Msps -
> giving the sample rate of I/Q 32Msps.

> Is that correct so far?

Yes.

> I am unsure what the minimum interpolating rate of the CIC is, or the
> maximum for that matter.  Can anyone answer?

It's probably 1 or 2, though I doubt it's been tested.  The (workable)
maximum is determined by the width of the intermediate stages of the
CIC.  I believe we're good to 128 in the FPGA CIC.  Matt would know
for sure.

> Who sets the interpolation rate of the CIC internal to the FPGA to get
> from the specified number of samples per symbol from a modulator block
> in GNU Radio to a number that the CIC can interpolate into 64Msps?

The code in usrp_standard.cc controls the FPGA interpolation rate.
The rates do not have to be powers of two.  From the user point of
view the net interpolation rate must be in [4, 512] and a multiple of 4.

This is all controlled in usrp_standard.cc.  I suggest that you take a
look at it ;)

> Or is a modulator block required to do things in powers of 2 when
> connected to a USRP?

No.  You might want to start looking at for example, the gmsk
modulator/demod: gnuradio-core/src/python/gnuradio/blksimpl/gmsk.py

> Thanks,
> Brian

Eric




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