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[Discuss-gnuradio] Re: A low-budget SDR - Was: PCIe know-how?

From: ceriel
Subject: [Discuss-gnuradio] Re: A low-budget SDR - Was: PCIe know-how?
Date: Tue, 6 Mar 2007 22:46:49 +0200

On 3/6/07, Brian Padalino <address@hidden> wrote:
On 3/6/07, address@hidden <address@hidden> wrote:
> Yeah, that indeed is an important issue that needs a very detailed and
> thought-out solution. One thing I'd like to be able to do some day is
> have maybe three of these devices all 100 meters from my computer
> arranged in a triangle and then triangulate signals using the Time of
> Arrival principle. I might be able to eventually construct an antenna
> array that isn't just directional, but also aware of distance. 65Msps
> wouldn't be enough for useful resolution, but it's a start. :)
> I would have to co-ordinate the receivers exactly to do this... Could
> it be possible to supply a stable clock over Ethernet? Couple it to
> the -48VDC? =)

I highly doubt that you can do it over ethernet, but you may be able
to supply a 10MHz reference clock over a coax line that could drive
some sort of PLL that were highly stable?  I am not a clocking expert,
so you're a bit on your own.

> I think that, realistically, I will have to do something with the data
> already at the FPGA. Be it pre-processing or decimation I do not know
> yet, nor can I guesstimate due to lack of experience. PA3FWM in the
> link Henry posted managed to deal with 2.5Msps, but I don't know his
> bit rate. I've decided in the past that I would be happy with being
> able to see just 1MHz of bandwidth at the time, and PA3FWM seems to
> have exceeded that. The benefit of using a high-speed ADC in this case
> would not be voided, since we could still do a lot of mojo that one
> can't do with a radio that requires a tuner. The lack of tuner in
> itself makes the device cheaper too...
> And what's "RBW"? =)

Resolution Band Width - how accurate your FFT bins are.

> --
> Nos

On a side note - have you thought about trying to figure out what you
want to do in a simulation environment?  It might be worth while to
simulate a channel that has your desired signals in it, and see how
feasible it would be to actually accomplish such a thing.

Moreover, if you plan on having your entire front end open, have you
thought about the consequences of large signals saturating your ADC
and not allowing the rest of your band in?  Without a tuner and
filters, you are going to be a bit more susceptible to saturating your
ADC - possibly with unwanted signals.

Yes, I thought about simulations today. Apparently Verilog is designed
to facilitate that aswell.
Should I do these simulations with for example Altera's Quartus II?

And indeed I've thought about saturating the ADC. I first thought
about a varistor for the sole  purpose of protecting it from voltage
spikes, but I realized that it could cause clipping, which would look
like overmodulation and could drown signals in noise.
One of the High Speed Data Transfers videos behind the link I posted
in the blog mentions a circuit I could use to condition the input
before it reaches the ADC, and it also mentions a balun very, very
briefly. I think of all of this as the RF frontend, and a problem I
don't need to solve yet. The RF frontend should be designed to allow
for undersampling too, so it's far from straight-forward. I think I'll
be designing it or looking for existing designs as the last thing,
because it is so important.


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