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Re: [Discuss-gnuradio] USRP packet parsing

From: Eric Blossom
Subject: Re: [Discuss-gnuradio] USRP packet parsing
Date: Fri, 23 Mar 2007 15:21:03 -0700
User-agent: Mutt/1.5.9i

On Fri, Mar 23, 2007 at 02:45:54PM -0400, Thibaud Hottelier wrote:
> Eric Blossom wrote:
> >On Thu, Mar 22, 2007 at 03:33:08PM -0400, Brian Padalino wrote:
> >>On 3/22/07, Thibaud Hottelier <address@hidden> wrote:
> >>>I can copy the sample to a fifo, but I still have 3 processes that want
> >>>to use the RAM a the same time: One to progressively store the packets
> >>>coming from the usb bus, one to copy the samples into the corresponding
> >>>channel fifo and one to copy the subcommands to be executed now. So, if
> >>>I am not mistaken I will have to find a way to synchronize the two last
> >>>processes, right?
> >>The FX2 will be writing into a FIFO that stores all packets
> >>intermingled with each other - be it either channel data or control
> >>data.
> >
> >Agreed.
> >
> >>A read process on that FIFO can separate out the channel data to be
> >>stored into separate channel FIFOs - one FIFO per channel that is
> >>implemented.  That same process can also put the control data into a
> >>control FIFO.  Only one of those is needed.
> >>
> >>That's 1 writer and 1 reader on the direct FX2 -> FPGA link.
> >
> >Yes.
> >
> So, let me summarize:
> One dual clock fifo (usb_fifo) to buffer the packet from the FX2. One 
> process store the data from the usb while one other process read them 
> and splits commands (stored in cmd_fifo) from data (stored in 
> chan0_fifo, chan1_fifo, etc). The data in chanX_fifo would be stored 
> like this:
> :            :
> |  sample 2  |
> |  sample 1  |
> |  #samples  |
> | timestamps |
> +------------+

I assume that you just copy the received USB packet (including the
8-byte header) into the channel FIFO.  The underrun processing really
needs to be handled "next to the DACs" and is a function of the
current state of the channel, the state of the fifo and the S & E
bits in the header.

> For each channel fifo, a process would wait for the timestamps to match 
> the time register and then write the next <#samples> to the 
> corresponding channel transmit chain at every tx_clock tick. 

Actually, the timestamp specifies the time that the sample is supposed
to hit the DACs, not the time that it enters the signal processing pipe.
This may take some thought to implement correctly, since the latency
through the pipe varies depending on the details of the pipeline and
the interpolation factor.

> So we end up with (#channel + 1) fifos.

  1 usb_fifo
  1 cmd_fifo
  N chanX_fifo

> The problem I see is that between to block of samples in the fifo, there 
> will be some processing delay to read the next timestamps and the 
> #samples. That's why I added a fifo between the usb_fifo and the 
> chanX_fifo in the diagram on the wiki. Is that a real problem?

I don't think it's needed.  Can you say more about why you think it's
needed?  Remember that the master clock is running at 64MHz, and the
packets are coming in at at most 32MB/s.


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