[Discuss-gnuradio] Re: USB FIFO

[Brian Padalino]

On 3/29/07, Thibaud Hottelier <address@hidden> wrote:
> I CC'd the list, so Eric can participate to this discussion.

The more the merrier.

> Yes but the only dual clock fifo is tx_usb_fifo, right? For this one we
> can use the Altera dual clock fifo. The only fifos that need the skip
> command are the tx_chan_fifo_X. I'm confused...

This is my understanding of the current way things work, and how we
can work off that.

The FX2 is setup to transfer 512-byte packets to the FPGA whenever it
gets one in that is destined for the FPGA (as determined by which
endpoint it is sent to).  The DMA process does this pretty quickly and
is already automated.

The FX2 directly writes to a single side of a large FIFO within the
FPGA.  Currently, there isn't any padding that gets stripped from any
packets anywhere.  There is obviously some packet space within the
in-band signaling spec that we don't need to send on through the TX
chain.

Here is the order I was thinking:
 - FX2 receives packet to be sent to FPGA
 - FX2 sends entire 512 byte packet to the FPGA
 - FPGA has state machine to process the packet which does the following
   - Check to be sure it can figure out where the packet has to go
   - Check to be sure the FIFO is not full
   - Read the length of the packet
   - Fill up the receiving FIFO until it is full or total length of
packet has been reached
   - If the packet length was reached (which might be less than 512),
skip the rest since it's padding
   - Else if the FIFO is full, loop and fill the FIFO until the
packet length has been reached
 - FPGA has cmd and channel state machines which do the following
with the tx_cmd and tx_channel FIFOs
   - Read out timestamp and length from packet
   - Ensure timestamp is in the future
   - If timestamp is in the past, skip the rest of the packet and set
appropriate flag
   - Else wait until the current time is reached
     - If current time is reached, send out the size of the packet

So there are really 2 different places we need to try to skip ahead -
the first is at the tx_usb_fifo because we'll be performing the
padding elimination there.  The second is within the tx_channel_fifo
and tx_cmd_fifo so we don't have to read packets that we're simply too
late on.

If any of that doesn't make sense, or people see it in a different way
- please feel free to comment and criticize.

Brian