[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Discuss-gnuradio] usrp_sink_s and other quick questions

From: Steven Clark
Subject: Re: [Discuss-gnuradio] usrp_sink_s and other quick questions
Date: Tue, 22 May 2007 12:06:44 -0400

Thanks for the clarification Eric. I was being a bit disingenuous by not revealing what I was really trying to do. I don't actually care what's being sent to the DAC. As I hinted at in an earlier email, what we've done is create a custom verilog load that takes the data lines after the FIFO but before the CIC filter and routes some of them out to IO pins on the daughtercard (which seem to be 0-3.3V LVTTL levels). The output of the DAC is of course nonsensical, but you'd just set its gain to the min and ignore it.

So we have created a sort of "poor-man's digital sink".

Using this, yesterday some coworkers and I successfully integrated/synchronized a gnuradio demodulator (GMSK) with an external hardware bit-error rate tester. Now we are characterizing BER vs Eb/No...hopefully I can create a write-up of our experiences/results and share it with the gnuradio community.

Thanks for the support.


On 5/22/07, Eric Blossom <address@hidden> wrote:
On Mon, May 21, 2007 at 04:19:58PM -0400, Steven Clark wrote:
> If I need pin-level access to the DAC chip, sink_s is my only option AFAIK.
> I understand that it's interleaved I&Q, don't worry about that.
> My original questions remain.
> On 5/21/07, Eric Blossom <address@hidden> wrote:
> >
> >On Mon, May 21, 2007 at 10:48:04AM -0400, Steven Clark wrote:
> >> Hi all-
> >>
> >> Several quick questions.
> >> 1) For usrp sink_s, which bit of the short activates the MSB of the DAC
> >> chip? I.e., if I send 0bABCDEFGH IJKLMNOP, where each letter is either a
> >1
> >> or a 0, which letter matches the MSB?

What you sent to sink_s doesn't go directly to the DACs, but rather is
first interpolated and possibly upconverted.

See http://gnuradio.org/trac/wiki/UsrpRfxDiagrams

The DACs run at a constant 128 MS/s.  They are fed from the FPGA at
32 MS/s, and are interpolated by a factor of 4 in the AD9862.  See the
AD9862 datasheet for details.

The I & Q data written to sink_s should be 16-bit 2's-complement
host-endian data in the range -32768 to 32767.  The max and minimum
values that make sense actually depend somewhat on the associated RF
daughterboard.  Analog clipping may occur at values smaller in
magnitude than +/- 32,767.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]