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Re: [Discuss-gnuradio] Recovering x(t) from IQ samples

From: Jeff Brower
Subject: Re: [Discuss-gnuradio] Recovering x(t) from IQ samples
Date: Sat, 18 Aug 2007 23:24:31 -0500 (CDT)
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>> On Fri, Aug 17, 2007 at 05:23:06PM -0600, Bahn William L Civ USAFA/DFCS 
>> wrote:
>>> Q1) One of the formats in which I can send data to the USRP is as IQ data. 
>>> What does the USRP do with IQ data
>>> pairs? In the USRP documentation there is a block diagram of the Digital 
>>> Down Converter, but there is no diagram of
>>> the Digital Up Converter.
>> It is exactly the opposite of the DDC. ...
> I'm not sure if this is pertinent for your project, but there is code that 
> does just this in the FPGA, in the MRFM
> project in GNU Radio.  This is not the usual FPGA code that runs in the USRP, 
> but it can run in the USRP.  This code
> implements the block diagram at
> http://www.research.cornell.edu/KIC/events/MRFM2006/pdfs/Jacky%20talk/jacky-talk.html
> in the slide labelled Heterodyne control.  The block labelled DUC does the 
> upconversion, reconstructing x(t) from I
> and Q.
> The DUC in this code is not the DUC used by the usual USRP FPGA code, which 
> (as I understand it) uses a built-in DUC
> in the Analog Devices chip.   For our application, we need to synchronize the 
> DDC and DUC exactly.  The only way to
> do that was to put the DUC in the same FPGA program as the DDC.
> This FPGA code is in the respository at
> http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/toplevel/mrfm
> The Verilog code in mrfm_proc.v describes the block diagram discussed above.

Yes -- if you can exactly synchronize another complex multiply with the first 
one, then there is no ambiguity.  Just
like FFT/iFFT.  But so far William is trying to avoid programming the FPGA.  
I've already pointed out that if he's
willing to do this, then he can disable the downshift (complex multiply) and 
not have to deal with I-Q data in the
first place.  Or, he could modify the host buffer format to include two data 
streams, I-Q and original ADC data.

I don't know why programming the FPGA should look like a black hole.  Verilog 
is straightforward, Matt's code is well
structured and seems fairly well commented, there are tons of examples on 
Altera's website, etc.  Sometimes I think
people take "do everything in Linux software" to an extreme.  There's a reason 
Altera, Xilinx, Texas Inst, sell more
chips every year, even though Intel has tried for 15 years now to create a 
world without those guys.


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