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Re: [Discuss-gnuradio] Re: tx_chain - Verilog question


From: Brian Padalino
Subject: Re: [Discuss-gnuradio] Re: tx_chain - Verilog question
Date: Fri, 30 Nov 2007 17:20:06 -0500

On Nov 30, 2007 5:01 PM, Ronald Jetli <address@hidden> wrote:
> Hi,
>
> I do understand that there are "always" statements in the base code and the
> flow of those base code is clear to me.
>
> It is just this top module, whose logic is not clear to me. I tried writing
> a test bench, but that didnt help either.
>
> It would be great if anyone could spare a minute and throw some light ?

This is just wiring a couple things together to get the transmission
chain to work at the full clock rate.  There are 3 main components
here: a phase accumulator, a CORDIC and an interpolating CIC filter.

The baseband signals are fed into the CORDIC along with a phase from
the phase accumulator.  For each sample that goes in, the phase
accumulator rotates.  This generates an IF that is mixed with your
baseband signal.

The interpolating CIC filter gets your baseband signal up to the
proper sample rate to feed the DACs.

To write a testbench, you would need to set the interpolation
frequency properly and if you wanted to use the CORDIC, that would
have to be setup properly as well for the phase accumulator.

You would then strobe your samples in at a rate of Fs where Fs is some
fraction of the total clock speed and Fs*interp_rate = the clock rate.
 You then have to strobe every Fs to send your samples through the
chain.

Hope this helps.

Brian




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