----- Original Message ----
From: Bob McGwier <address@hidden>
To: Mohammad Hamed Firooz <address@hidden>
Sent: Wednesday, March 26, 2008 3:02:01 AM
Subject: Re: [Discuss-gnuradio] new 802.11b receiver
Do you know Fehrouz Farhang-B? I am sure you must. He is an
acquaintance of mine. Are you in the Wireless Communications Lab or the
DSP Lab (Signal Processing Group)?
I have before, and I wish to recommend again, Fehrouz book on SDR
techniques to people here.http://www2.elen.utah.edu/~farhang/
Who is directing your thesis work? I want to remind you and everyone
else listening, that we will soon have the USRP2. It will definitely
support the 802.11b and
g. It would be good to have the code early so
we can make a plan on moving it to the USRP2 to support the full bandwidth.
I am looking forward to visit your department at some time in the next
few months. I hope to be able to meet you.
Thank your for doing this work!
Mohammad Hamed Firooz wrote:
> Quoting George Nychis <address@hidden
>> Brian Padalino wrote:
>>> On Mon, Mar 24, 2008 at 1:02 AM, Mohammad Hamed Firooz
>>>> As you may know, BBN guys have developed a receiver for 802.11b. But
>>>> due to the USB limitation, they had to cut the spectrum which
>>>> leads to
>>>> low SNR. We have developed a new receiver by doing some operation
>>>> (especially de-spreading) inside the FPGA (before sending data to
>>>> Therefore, our receiver use the whole spectrum to abstract the data.
>>>> you can find more information and the codes in our website:
>>> So, where's the Verilog for the changed FPGA build?
>> Considering the amount of research in 802.11 networks, I'm sure it
>> will be extremely helpful for someone in the future who might want to
>> modify your implementation for you to host the Verilog code... just
>> as Matt was nice enough to provide you his FPGA code for the USRP ;)
>> Maybe make it a separate archive that you are hosting.
>> Nonetheless, cool and thanks for sharing! I'm sure someone will poke
>> around with this.
>> - George
> Sure, I will probably post the Verilog codes by tomorrow. Right now, I
> am trying to make it more readable and neat. Sorry for the delay.
AMSAT Director and VP Engineering. Member: ARRL, AMSAT-DL,
TAPR, Packrats, NJQRP, QRP ARCI, QCWA, FRC. ARRL SDR WG Chair
"Debugging is twice as hard as writing the code in the first place.
Therefore, if you write the code as cleverly as possible, you are, by
definition, not smart enough to debug it." - Brian W. Kernighan
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