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Re: [Discuss-gnuradio] Reclocking URSP and phase imbalance

From: Eric Blossom
Subject: Re: [Discuss-gnuradio] Reclocking URSP and phase imbalance
Date: Thu, 5 Jun 2008 11:53:14 -0700
User-agent: Mutt/1.5.17 (2007-11-01)

On Thu, Jun 05, 2008 at 11:04:53AM -0700, Matt Ettus wrote:
> Gregory W Heckler wrote:
>> To the USRP experts out there:
>> I reclocked my USRP from 64 to 65.536 MHz and have recently discovered 
>> that the I & Q samples are no longer orthogonal, rather they seem to be 
>> only 70 degrees or so apart. I would guess this is due to some hard coded 
>> values in the CIC or HB filters? Is there a USRP command to correct for 
>> this phase imbalance? Thanks!
> That's an odd problem.  Sounds like a timing issue.  Keep in mind that the 
> ADCs are only spec'ed to 64 MHz and the FPGA image is compiled to meet 
> timing at 64 MHz.  You might need to recompile it with the stricter timing 
> numbers.  All of the DSP stuff in the FPGA should not care about the 
> absolute frequency as long as it meets timing.
> You also need to make sure that the tuning word sent to the DBSRX is based 
> on a 65.536 MHz reference frequency, not 64.


You can handle that last part by modfiying this line in usrp_basic.h
and recompiling everything:

   * \brief return frequency of master oscillator on USRP
  long  fpga_master_clock_freq () const { return 64000000; }


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