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Re: [Discuss-gnuradio] A Verilog question or two

From: Jason Uher
Subject: Re: [Discuss-gnuradio] A Verilog question or two
Date: Wed, 15 Oct 2008 09:30:19 -0500

2008/10/14 Daniel O'Connor <address@hidden>:
> On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
>> always @(posedge clk)
>> begin
>>  tap1 <= #1 input;
>>  tap2 <= #1 tap1;
>>  tap3 <= #1 tap2;
>> end
>> the #1 ensures that tap1 gets updated before tap2?
> According to what I have read with about synthesis tools the delays will be
> ignored totally.
> I see a lot of it though, so I don't know if it's superstition or the manual
> lies.

I think the delays are just for simulation.  In synthesis the
assignments take a real amount of time to complete (because it's
hardware).  If you are dependent on that delay, you need to signify
that in simulation, otherwise the assignment would occur at the same
simulation timestep as everything else and you could be using new data
instead of old.  Most likely synthesis ignores them, but they are
needed for the simulation (I'm not 100% sure, I usually remove all
such delays before synthesis testing).


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