Hi
after looking at the verilog code for some time, these are my results:
in module usrp_inband_usb, for each of the four aux adcs, the signal level is
read from the adc and an gliding average of the rssi and an saturation
indicator is is calculated. The rssi value is put but into the lower 16 bits
of an 32 bit bus, which is passed on through the module rx_buffer_inband and
reaches the module packet_builder.
In packet_builder, the rssi bus of the adc corresponding with the channel
which is transmitted is selected. Until here, everything is fine.
As said before, the rssi value is in the 16 lower bits of the rssi bus. When
looking at the calculation of the rssi value, it is apparent that it is a IIR
filter with output value in the range [0..0x7ff] (max value is determined by
the max absolute value of the aux adc, which is 0x7ff).
Now, the packet_builder takes the lower 6 bits of the 16 bit register with an
value range corresponding to 11 bits and puts it into the usb packet. So as
soon as the average value of the adc is higher than 0x3f (63), the rssi value
in the usb packet will be just noise.
Proposal:
Change the rssi value to a logarithmic encoding. With a 3.3 split, 10 bits can
be encoded, which is almost the range of the aux adc (11bit). Step size is
about 0.1dB.
A verilog module for encoding the rssi value is attached. I have no tools for
verilog, so I did not test it. Dont know if it works, and if the the changes
in the packet_builder for getting the log value from the linear value is
correct.
Would be nice if anyone could test this and pass an fpga firmware on to me.
Thanks,
Stefan
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