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Re: [Discuss-gnuradio] FPGA "headroom" in USRP2

From: Johnathan Corgan
Subject: Re: [Discuss-gnuradio] FPGA "headroom" in USRP2
Date: Mon, 9 Feb 2009 19:36:16 -0800

On Mon, Feb 9, 2009 at 6:25 PM, Marcus D. Leech <address@hidden> wrote:

> Is there room in the USRP2 for building a 2048 lag autocorrelator with 1
> or 2-bit sampling?

Most likely.  I did the investigation to implement a fully pipelined
2048 point FFT with 16-bit I/Q samples using the Xilinx core generator
software.  It looks like it would take up just under half the area in
terms of slices.  We're using about half the slices already, so this
would fill the rest of the chip.  I don't recall what the block ram
usage was, but we're already using most of those for the CPU/firmware.
  I don't know the effect of having 1- or 2-bit sampling instead of
16.  The Xilinx coregen docs are pretty good for this though.

You'd do an FFT on the input array, calculate bin power, then an IFFT
for the ACF output.  The FFT core would need to be shared between the
two operations, so that would cut your data rate in at least half, and
lose the ability to pipeline.

There could be an efficient time domain way of doing what you want,
depending on how often you wanted the results.


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