[Discuss-gnuradio] fpga verilog question

[Rushikesh Khasgiwale]

I am trying to transmit an ASK packet from the usrp fpga(verilog) without 
using usb data. I cant figure out where should I put the I-q data in 
verilog.

does anyone know what clock(rate) is used to transfer it to ad9862? I 
observed that the tx_sync signal decides whether data on tx_a[13..0] is I or 
Q.
I guess I could bypass the tx cic_interp filter since I'm generating data in 
the fpga. would this allow me to write the I-q data directly to the pins?

I use C++ functions, to set the frequency,mux, enable daughter board.

thanks
-rushikesh