RE: [Discuss-gnuradio] ISE11.1 error using Linux CLI..Update HELP

[Craig Kief]

Jeff,
I would say to open a thread. I have a man loading up 11 here and maybe we
can provide a little insight.  Like most, we have kept with 10 for a long
time because by SP3 it is pretty stable.  From years of working with Xilinx
I would strongly recommend that you have all the service packs updated.
Xilinx has had some really rough times in the past year and 11 (when it
first came out) might not have been their greatest work.  Anytime you have
to do almost 1G of service pack, that fixes a lot of stuff.
Craig



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-----Original Message-----
From: address@hidden
[mailto:address@hidden On Behalf
Of Jeff Brower
Sent: Tuesday, January 19, 2010 11:36 PM
To: Matt Ettus
Cc: address@hidden
Subject: Re: [Discuss-gnuradio] ISE11.1 error using Linux CLI..Update HELP

Matt-

> We are currently working on a fix for the problems with compiling
> under the ISE 11.  We believe it to be a problem with ISE 11,
> since the design works fine under ISE 10, but have not gotten
> very far.  Any help anyone can provide on this would be much
> appreciated.

I didn't see ISE 10 vs. 11 threads currently active on comp.arch.fpga, but
if you guys start one please mention so we
can follow along and possibly contribute in some way.  We're not using ISE
11 yet, but we do a lot of ISE and Xilinx
FPGA work.

Thanks.

-Jeff

> On 01/18/2010 05:38 AM, Mahesh Poolakkaparambil wrote:
>> Hello ,
>>
>>                I have posted a query on the forum regarding "compiling
>> address@hidden on ISE11.1 ", I still could not find a good remedy for this. 
>> I am
attaching the error message with this
mail. i hope this will help form some one to help me regarding the problem.
>>
>>
>> Compiling verilog file "../../u2_core/u2_core.v" in library work Module
<atr_controller> compiled
>> Compiling verilog file "../u2_rev3.v" in library work
>> Module <u2_core> compiled
>> Module <u2_rev3> compiled
>> No errors in compilation
>> Analysis of file <"u2_rev3.prj"> succeeded.
>>
>>
>> =========================================================================
*                     Design Hierarchy
Analysis                         *
=========================================================================
ERROR:HDLCompilers:87 - "../../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" line
134 Could not find module/primitive
'fifo_xlnx_2Kx36_2clk' ERROR:HDLCompilers:87 -
"../../../eth/mac_txfifo_int.v" line 35 Could not find
module/primitive 'fifo_xlnx_512x36_2clk'
>> -->
>>
>>
>> Total memory usage is 131520 kilobytes
>>
>> Number of errors   :    2 (   0 filtered)
>> Number of warnings :    0 (   0 filtered)
>> Number of infos    :    0 (   0 filtered)
>>
>>
>> Process "Synthesis" failed
>> INFO:TclTasksC:1850 - process run : Generate Programming File is done
>>
>>
>> I hope to hear a remedy for this problem,
>>
>> Once again thanks in advance,
>> Mahesh





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