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Re: [Discuss-gnuradio] Auxiliary ADC


From: Eric Blossom
Subject: Re: [Discuss-gnuradio] Auxiliary ADC
Date: Fri, 22 Jan 2010 09:00:00 -0800
User-agent: Mutt/1.5.20 (2009-08-17)

On Fri, Jan 22, 2010 at 09:24:24AM -0500, Doug Geiger wrote:
> >
> >At this point, firmware in the USRP2 controls the daughterboards, and
> >the read_aux_adc functionality is not exported to the host.
> >
> >Eric

Hi Doug!

> Does the firmware currently do anything with the Aux ADC? I see the
> definitions for reading from the SPI controller, and the function
> (firmware/lib/lsadc.c: lsadc_read_rx(int)) which appears to be the
> only place that reads from the correct SPI device.

We confirmed that it worked :-)

> Also, it looks
> like it would be difficult to read the value directly from inside
> the FPGA: i.e. if I wanted to use the RSSI value for an AGC or
> squelch control, I'd probably be best served by periodically reading
> the value from within the firmware, and pushing it back into a
> register in, e.g., dsp_rx_regs. This would likely mean I'd have some
> additional inherent delay in using the value in the DSP chain. Is
> there a better way - e.g. I assume it would be possible to load the
> data from the SPI controller in the FPGA, but does that come with a
> (much?) larger cost in terms of logic, and therefore area/etc.?

There's a plan/idea to implement closed loop AGC in the fabric of the
FPGA.  Part of that would entail moving the relevant SPI signals off
of the wishbone peripheral and directly into the fabric.  We would
probably run the loop at something in the neighborhood of 300kS/s to
1MS/s, corresponding to the usable bandwidth of the low-speed ADCs and
DACs. 

To handle all the d'boards there are a few variations that need to be
dealt with.  There are about 3 ways that the daughterboards control
the gain.  There are about 2 ways to sense the RSSI of the incoming
signal.  Some d'boards provide an analog signal we can read with the
low speed ADC, others have nothing, so we'd have to use the output of
the high-speed ADC to sense.  We'd need to implement suitable
approximations of fixed point exp and log in the FPGA[1], then we need
a couple of different variations in the control loop depending on
whether or not the inputs and outputs are already in log form or not.
We'd also need registers to control the loop gain and reference set
point.

If you're so inclined, please feel free to give it a shot.  I know
that Matt, Tom Rondeau, Johnathan and I have all given this some
thought, and between us, we can probably help sort it out.

> Thanks,
>  Doug

Eric

[1] "Elementary Functions: Algorithms and Implementation, 2nd Ed",
    Jean-Michel Muller




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