Re: [Discuss-gnuradio] 16 digital I/O lines to control external devices like antenna switches

[Matt Ettus]

On 05/21/2010 06:33 AM, Harley Myler wrote:
> I traced those from the WBX simple GDB, through the WBX and to the
> USRP2. They wind-up at U1 (XC3SXX00FG456−IO7(tx)) and U1
> (XC3SXX00FG456−IO2(rx)) on page 3 of 8 of the USRP2 schematic. I do
> not know why they are both labelled "U1". The date, revision and
> drawn-by blocks only had tokens. I may be looking at a preliminary
> schematic.

It's a 456 pin part, which would be huge if it wasn't split up.  The 
actual part number is XC3S2000-5FGG456.  The XX in the part name in the 
schematic is because the 1000, 1500, and 2000 are all pin compatible.


> So at this juncture my assumption is that the FPGA(s) given by the
> XC... labels above, although I cannot find a Xylinx part number
> match, simply run out to the 20 pin header connector on the
> daughterboard. Of the sixteen lines, each daughterboard usurps--an
> ironic term here--any number of the available 16 GPIOs for their own
> purposes and what is left are available to the user.

Yes.

> As such, my conclusion is that the following, per the schematic, are
> available:
>
> RX Control Pins io_rx[15:14] −− Unused TX Control Pins iotx[15:8] −−
> Unused

IO_RX[15]       RX antenna selector pin
IO_RX[14]       Available
IO_RX[13:8]     RX attenuator control
IO_RX[7]        RX 5V supply enable
IO_RX[6]        RX 3.3V supply enable
IO_RX[5]        Available
IO_RX[4]        RX baseband amp enable
IO_RX[3]        RX PLL Chip enable
IO_RX[2]        RX PLL power down
IO_RX[1]        RX PLL mux for debug
IO_RX[0]        RX PLL lock detect

IO_TX[15]       TX/RX switch
IO_TX[14]       Available
IO_TX[13]       Available
IO_TX[12]       Available
IO_TX[11]       Available
IO_TX[10]       Available
IO_TX[9]        Available
IO_TX[8]        Available
IO_TX[7]        TX 5V supply enable
IO_TX[6]        TX 3.3V supply enable
IO_TX[5]        Available
IO_TX[4]        TX mixer enable
IO_TX[3]        TX PLL chip enable
IO_TX[2]        TX PLL power down
IO_TX[1]        TX PLL mux for debug
IO_TX[0]        TX PLL lock detect



> This gives 9 GPIO pins available to the user, hardly 16. The product
> documentation should reflect this. Nevertheless, nine will be
> adequate for my purposes.

I count 10 in the above list.  The WBX docs never say there are 16 pins, 
as far as I can tell.  It is the USRP and USRP2 documentation which 
states 16 pins are available, and they are.

Matt