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Re: [Discuss-gnuradio] Phase Lag in USRP Output Signal

From: Balijepalli, Arvind
Subject: Re: [Discuss-gnuradio] Phase Lag in USRP Output Signal
Date: Thu, 3 Jun 2010 13:36:50 -0400

On Jun 3, 2010, at 12:33 PM, Matt Ettus wrote:

> On 06/03/2010 05:06 AM, Balijepalli, Arvind wrote:
>> Hi all, I plan to use the USRP to run a feedback controller. The
>> basic idea is to read in a feedback signal over three input channels
>> (two LFRX daughter boards), process them to generate control signals
>> that are output over three DACs (using two LFTX daughter boards). All
>> of the processing will take place in the FPGA and I don't plan to use
>> the decimation and demodulation/modulation stages that are part of
>> the default GNURadio FPGA code.
>> However to begin with, I would like to measure the latency of the
>> USRP. To do this, I read a single input channel using the LFRX
>> daughter board and output the same value over the LFTX daughter
>> board.
>> The FPGA code itself is very straightforward in this first pass. I
>> started using one of the top level FPGA code images and cut out the
>> parts I wouldn't use. My code simply scales the input to 14 bits by
>> bit shifting by 2 and writes it to the output. Here's the relevant
>> code fragment:
>> always @(posedge clk64) adc0<= #1 {rx_a_a, 2'b0};
>> assign tx_a = adc0;
> With the default settings, the DAC is accepting data at 32 MS/s 
> interleaved.  You can change that with settings for the AD9862.
>> I have setup the ADC and DAC using the python call
>> _write_9862(which_codec, regno, value) with the following values: RX
>> Side: Rx mode:               Single channel ADC signal Data Type:            
>> unsigned ints
>> (2s complement turned off) PGA Gain:         minimum
>> TX Side: Tx mode:            Single channel DAC data Data Type:              
>> unsigned ints
>> (2s complement turned off) PGA Gain:         maximum
>> The problem I see is that the output from the FPGA has a phase lag of
>> 180 degrees in relation to the input. As far as I can tell, the
>> ADC/DAC and the FPGA are setup correctly and my function generator
>> and scopes are set to 50ohm impedance.
>> Has anyone seen this before?
> Have you disabled the TX coarse and fine mixers in the AD9862?  Even if 
> you set their frequency to 0, they will still have a fixed rotation 
> unless you disable them.
> Matt

Thanks for your reply. The problem seems to be mostly solved now, I'll explain 
below, but to first respond to your suggestions/questions. I changed the DAC to 
accept non-interleaved data, which I presume should be at 64 MS/s. I setup the 
interpolator on the Tx side to 2x to then bring it up to 128 MS/s. I am not 
sure how to disable those mixers exactly. The only coarse-fine settings I see 
are for gains (maybe these somehow control the mixing?) which I have set to 0.

The way I fixed the phase lag I was seeing was to setup the DAC to accept 2s 
complement data and then provide it signed integers. I changed the verilog code 
where I assign the output from

always @(posedge clk64)
     adc0 <= #1 { rx_a_a, 2'b0};


always @(posedge clk64)
     adc0 <= #1 ( ~({rx_a_a, 2'b0}) + 14'b00000000000001 );

Unless I am completely missing something which is possible, the DAC seems to 
like signed integers. With this change, the latency between the inputs and 
outputs is approximately 400ns, with timing jitter less than ~4ns.

On a related problem, I see that the USRP is loading the input of the function 
generator. I have turned off buffers and stages of the ADC that I don't use 
according to the ADC documentation. Also, my input signal is never greater than 
100 kHz, so I don't think this is an impedance matching problem.


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