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Re: [Discuss-gnuradio] Alternative Hardware

From: Marcus D. Leech
Subject: Re: [Discuss-gnuradio] Alternative Hardware
Date: Mon, 10 Jan 2011 12:59:27 -0500
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On 01/10/2011 08:23 AM, Patrick Strasser wrote:

* Have a look at Digilent [1] Basys and Nexsys boards. You get the same
interface chip as the USRP, which should give a good start for firmware
development, and a FPGA, switches, buttons, displays, connectors
(VGA/PS2 etc.) for about the same or less price. Academics/Students get
it cheaper.
Moreover Digilent offers a number of modules to connect, with examples
and schematics.
If you really want high sampling rates and frequencies, have a look at
the Charleston SDR [2].
Oooh, the Charleston SDR is within about 5-6dB(Msps) of what I'd like in a cheaper
  hardware alternative.

You know, a "reasonable" project for some C++ keener on this list would be to write a UHD driver interface for the Charleston SDR system, and open-source
  the results.  Might even make a not-bad undergraduate project.

But since we're on the topic of alternative hardware, I'll throw in my ***PERSONAL**** two-cents about this. I think that there are a couple of different "forks" to this. There are experimenters who do Rx-only (I'd say perhaps more than half of the folks on this list), for whom a less-functional hardware system (and presumably less costly) would be "reasonable". For experimenters who want to do Tx, they also overwhelmingly-likely want to do Tx/Rx, and for that, it would be hard to beat what is already out there (although, I'm willing to be convinced otherwise).

For an Rx-only "solution", I'd want:

   o Integrated RF down-conversion chain
o It would be hard to get much better than what the WBX uses here, based on the ADL5387 (quadrature mixer) and ADF4350 (PLL synthesizer). Such a "line-up" would give coverage from 68.75MHz to 2.2GHz.

o Ability to use external 10MHz reference both for PLL and sampling clock. o One might simplify this to use an external 40MHz reference that is used directly for the sampling clock, and /4
                  for the PLL.

o Perhaps a switch-in upconverter that converts HF up to a convenient IF (70MHz, 100MHz??) for the ADL5387/ADF4350 stage.

   o 40Msps ADC
o possibly one with built-in DDC and decimation hardware, with the proviso that it support full-rate (no decimation). The one used by the Charleston SDR has the right overall architecture,
              but supports a maximum bandwidth of 2.5Msps complex.
           o possibly variable sample rate

   o A convenient computer interface
o I'd prefer 1GiGe, so that I could "deliver" the full 40Msps (with reduced sample sizes) to the host computer.
           o USB would be acceptable.

Notice that there's no FPGA shown here. My hope is that there's something similar to the TI parts used by the Charleston SDR, but
  allowing higher bandwidths (lower decimation).

An alternative (that still doesn't require an FPGA) is to have switchable baseband filters on the output of the analog front-end, covering various "useful" bandwidths. These would have to be fairly "stiff", to allow a lower sample rate to work properly. I wonder if SCFs (Switched-Capacitor Filters) exist that cover these bandwidths (let's say, 2.5MHz to 20MHz). My off-the-cuff proposal for such a scheme
  would be four discrete filters:

      o 20MHz    (40Msps)
      o 10MHz    (20Msps)
      o 5MHz      (10Msps)
      o 2.5MHz   (5Msps)


Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium

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