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Re: [Discuss-gnuradio] Split-function implementation of 802.11g OFDM PHY

From: Nemanja Trecakov
Subject: Re: [Discuss-gnuradio] Split-function implementation of 802.11g OFDM PHY and MAC on USRP2
Date: Sun, 14 Aug 2011 21:23:29 +0100

Josh and Nick, 

thank you very much for your reply.

I have some more things to ask:

> >> 1) The external SRAM is currently used for buffering TX packets
> >>
> >> 2) The existing makefile is really for unix installations. You will have a
> > much easier time compiling your custom image with a Linux ISE
> > installation.

@Nick: I am aware that the existing makefile is for unix-like installations.

However, I have only the windows version available at the moment.

> You should be able to do this on windows too. You just need to install
> gnumake, and Xilinx xtclsh should be in your %PATH%

@Josh: I copied the FPGA UHD source code to my windows machine and installed 
gnumake. At first I didn't know how to run gnumake, so I tried the command 
promt and run 'gmake' command the top\USRP2 directory. Please correct me if I 
did this wrong, but the output saw quite correct, since it started to build and 
gave the error of that 'xtclsh' is not found/recognized. I did not include it 
in the %PATH% because I did not know how to do it. I used search in windows and 
found two files named 'xtclsh'(both recognized as application files by windows) 
in Xilinx ISE directory. So my question is:

- HOW TO INCLUDE xtclsh IN MY %PATH%? Where and how(form of it) to write the 
path towards the files I found? 
I saw your "recipe" from before on 
(http://old.nabble.com/xtclsh-not-found-td30486735.html#a30486735), but I am 
not sure how to do it in windows.  
- WHICH FILE TO USE? - ...\ISE_DS\ISE\bin\nt   or the in 

> >> 3) Generally no. Use a firmware image version that corresponds to your FPGA
> > image though.
> >>
> >> 4) UHD API refers to the host (PC side) interface. If you're reading RSSI
> > from the FPGA it doesn't apply to you.
> >

@Nick: I understand that it doesn't apply to my project directly, but I am just 
curious on the ways that it's possible to read RSSI in the software (explicitly 
what to write where and how to run, since I am a newbie)

- Can you explain how I can read RSSI in general, irrelevant of my project? 

As I understand, there are two alternatives:

1) If daughterboard having analog RSSi output -> own dedicated small low-speed 
ADC -> FPGA -> host
2) IF of received signal -> usual big high-speed ADC -> FPGA ->host

- To which alternative does 'rssi.v' file in uhd\fpga\usrp2\sdr_lib 
directory correspond to?

- How do we adjust dynamic range of ADC to the incoming signal?

Since I want to implement a simple carrier sensing in the FPGA, I would like to 
know how I can read the value of the analog RSSI after being digitalized with 
ADC and the form of the signal, in order to empirically find the limit for idle 

Thank you in advance!

Best Regards,
Nemanja Trecakov


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