On 01/09/2011 1:08 PM, Nick Foster wrote:
In the specific case of GPS, most active GPS antennas (which is what
most people use) have GPS-optimized LNAs with very low noise figure,
On Thu, Sep 1, 2011 at 8:42 AM, Wolfarth,
I am generating my masters thesis proposal and I have a few
questions about the capabilities of the E100 and the
feasibility of my project. I have read other posts to gather
information, but correct me if anything I've determined is
wrong. My goal is to implement an 8 channel GPS L2C receiver
on an FPGA. I am interested in doing this with the E100 since
I may be able to take advantage of the ARM processor as well.
Can anyone with experience in this area provide advice?
I would like to use the RFX1200 to receive the L2C signal
since it has better performance characteristics than the
DBSRX. This would prevent me from first acquiring L1 signals
to aid in acquisition, so I propose using preloaded almanac
data to estimate SV position/Doppler frequency. This would
reduce the number computations when acquiring L2 CM code. The
end result only has to go as far as to decode the navigation
bits: I will not need a position solution.
The root of my question is: does the FPGA on the E100 have
enough space to handle this project?
Does it sound like I'm on the right track?
Sounds like a very interesting project. I have two
1. The SBX daughterboard has a better noise figure (5dB vs.
8dB typ.), with better linearity, and would be better suited
for GPS work, especially if you aren't using front-end
filters. SBX will also receive both the L1 and L2 frequencies.
and easily enough gain to swamp the noise figure of whatever
receiving hardware is downstream, so the noise figure of the
board is largely irrelevant in most cases with GPS active
In my radio astronomy work (where Tsys is absolutely critical), as
long as the downstream receiver has a noise figure below about 15dB
so, I generally don't care what it is, since I use a tuned vLNA in
front of it. It's a very similar situation with GPS.