>The DDC chain follows the same basic rules, but rather, it is controlled
>by issuing stream commands. So when a receive burst is ended, the CORDIC
>phase will also reset back to zero.
Okay. If I understand you correctly, then if I have a GRC flow-graph which consists of both uhd usrp source and uhd usrp sink then both receive and transmit part of the flow-graph will be streaming samples indefinitely. That is, the uhd usrp source keeps on receiving samples from fpga and uhd usrp source keeps on sending samples to fpga until I kill the flow-graph. Now, if I manage to send bursts equipped with tags, the transmit side operates in "send N
samples and done" mode but the receive side of the flow-graph should still be running in continuous mode. That is only the DUC cordic will reset but not the DDC cordic (in my case). Am I right?
>The step size of the RF frontend depends on the synthesizer on the
>daughterboard, the reference clock (from the motherboard), and frequency
>requested. Its not possible to give a general rule. But the driver can
>tell you what is possible.
>If it helps, boards like RFX use integer N synthesizers, so the step
>size is rather large, several MHz. Boards like SBX and WBX use
>fractional N, the step size is on the order of kHz.
Okay. I have done the following:
set receive center RF frequency to 892MHz, actual RF frequency was 892857142.857.
set receive center RF frequency to 896MHz, actual RF frequency was 896428571.429.
I then took the difference 896428571.429 - 892857142.857 which was
3.571428572 MHz. So, it means ~3.5 MHz is the step size for my SDR (RFX900 + USRP N200). Right? But that step size is not an integer value. Isn't it weird?
Thanks for the help.