I am trying for quite some time to tweak M&M synchronizationi block, but the problem is I have a lot of single bit errors, and I suppose it shouldn't be like that because signal I am providing is almost ideal. Here are some important features of the communication itself:
- data is encoded using differential manchester code
- modulation scheme is FSK with frequency deviation of arround 75KHz
- symbol rate is 19200 KBaud
I suppose for this simple communication protocol, I should have much better results. Frame starts with preamble, followed by 160 symbols, which is 10 bytes of data at the end. Preamble has following structure 10011001100110011001100110011010. The percentage of sucesfully received preamble is 1005, but then comes trouble.
Setup is following: usrp1 with sample rate od 507937 Sps (I set 512KSps but device doesn't support this rate), then comes bandpass filter, followed by quadrature demodulator and bit slicer. Bit slicer is connected to correlate access code block which is connected to modified framer sink block.
Here I provide output of my bit slicer (which I am proud of :)), and hope somebody of you guys can provide me advices based on your experience.