Re: [Discuss-gnuradio] Phase measurement with Ettus Research N210

[Marcus D. Leech]

On 06/17/2014 04:56 PM, Daniele Nicolodi wrote:
> I'll try to see if this makes a difference. The minimum sampling rate I
> can program is ~193 kHz (it is a strange fraction that I cannot check
> right now).
Minimum sample rate = 100e6/512

The USRP devices do strictly-integer decimation in the FPGA.


> Given your explanation I believe that the issue may come from finite
> accuracy in the generation of the 100 MHz sampling rate: how is the 100
> MHz clock generated exactly?  If the 100 MHz clock is divided with a DDS
> to be compared to the 10 MHz clock to derive the error signal for the
> PLL, the finite precision of the DDS control register may explain the
> small frequency error (a 32 bit DDS would introduce the right order of
> magnitude effect, but I haven't check the exact number).
>
> Cheers,
> Daniele
The master clock on the N2xx series is derived from a 10MHz source 
(on-board 10MHz VCTCXO, or external, or internal GPSDO), feeding an
  AD9510 PLL clock generator, which in turn controls a 100MHz VFO, 
implemented with a 100MHz VCTCXO--both clocks are in the 2.5PPM category.

http://files.ettus.com/schematics/n200/n2xx.pdf




--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org