If what you are trying to do is build a verilog test bench and use this data as stimulus then stay within GR, multiply your float data by 2^16 and then convert it to short integer before passing to file sink(s).
That will give you two's complement signed integer signal data.
Assemble your packet level tdata[63:0] from file data as follows (where I1/Q1 follows I0/Q0 in time):
[63:56] I0 MSB
[55:48] I0 LSB
[47:40] Q0 MSB
[39:32] Q0 LSB
[31:24] I1 MSB
[23:16] I1 LSB
[15:8] Q1 MSB
[7:0] Q1 LSB
If this block is expecting packetized data, rather than a simple sample stream then assume you already understand the packet header format you need to add also?
My tip for the day, especially since right now you are just building a loop back to bring up your test bench is generate simple waveforms entirely within your test bench. A saw tooth or triangle wave is incredibly easy to generate by incrementing a signed integer type, and visually easy to check in a waveform viewer.
In terms of number format, try to think of the integer data as Q1.15, not Q16. In otherwords 0x8000 represents -1.0 and 0x7fff represents 0.99999....when you actually analyze your DSP architecture it makes it easier to keep track of word growth knowing that 1.15+1.15 = 2.15 and 1.15*1.15 = 2.30