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Re: [Discuss-gnuradio] Multi-rtl - making multi-channel receiver out of

From: mleech
Subject: Re: [Discuss-gnuradio] Multi-rtl - making multi-channel receiver out of multiple RTL-SDR dongles
Date: Wed, 25 May 2016 15:36:58 -0400
User-agent: Roundcube Webmail/1.1.5

The AirSpy uses the R820T2 chip for the tuner, but a different sampling/DSP "engine".

Yes, making the charge-pump and "dither" mods will help with phase-coherence.

Somebody needs to "own" the rtlsdr driver, and merge in the last couple of years of field experience and branching that has gone on with it.




On 2016-05-25 15:04, Piotr Krysik wrote:

Hi Marcus,

I don't know much about AirSpy.

Does it use the same demodulator chip as current RTL-SDR dongles?
And does it mean that change to low level part of rtlsdr driver might
help to get rid of that frequency offset?


W dniu 25.05.2016 o 16:35, address@hidden pisze:

There are a couple of issues with the rtlsdr driver used by gr-osmocom
in this regard:


  (A) The charge-pump loop current is too constrained for the higher

  (B) The "dither" option appears to have a bias that causes a (small)
frequency offset.


The driver that AirSpy uses fixes both of these, although without
"dither", the tuning granularity is worse.  Not sure this matters.




On 2016-05-25 09:28, Marcus Müller wrote:

That, or simply, the output clock VCO changes its reaction to the
control voltage under certain circumstances (temperature, frequency) so
much that the control loop loses the ability to reach stationary
exactness (e.g. due to natural limits on the magnitude of the VCO
voltage). These devices definitely were made with cost in mind – not
with maximum reliability, and hence I can believe that for example with
the Elonics E4000 tuner, the charge pump used to generate the VCO
voltage simply might deteriorate with temperature.


On 25.05.2016 14:25, Sylvain Munaut wrote:

of the drift remains a mistery (probably due to the implementation
of the PLL,
but I cannot understand why Phase Locked Loops would drift in Phase !).
If the phase comparator is digital ( i.e. a XOR ) and the input clock
is somewhat analog, the gate thresholds might vary depending on
temperature, thus shifting the cycle a bit.

Just a thought.




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