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Re: [Discuss-gnuradio] Faster FPGA clock rates


From: Derek Kozel
Subject: Re: [Discuss-gnuradio] Faster FPGA clock rates
Date: Thu, 14 Jun 2018 11:03:03 +0100

Hello Maria,

Ettus, and a few other sources, supply FPGA based GNU Radio blocks, but they do not support the B210. The more fundamental issue though is that the AD9361 has a maximum sample rate of 61.44 MS/s, so FPGA acceleration will not help in increasing the rate above that maximum. If your application needs a higher rate then you'll have to look at a different radio.

Ah, Marcus has replied saying much the same things as I've been writing. You can find out more about the FPGA based architecture that is available on the larger Ettus radios at the links below, including GNU Radio integration.
https://kb.ettus.com/RFNoC
https://kb.ettus.com/Getting_Started_with_RFNoC_Development

Regards,
Derek


On Thu, Jun 14, 2018 at 10:30 AM, Maria <address@hidden> wrote:
Hi all,

I would like to know whether GNU radio can be used to program the FPGA of the USRP and hence assist with faster clock rates. I am using the USRP B210 and the maximum clock rate seems to be 61.44 MHz so I wanted to know if it is possible to increase that rate by programming on the FPGA and if that programming can be done through the GNU radio platform. If so, could you please let me know which programming language would I need? Python, C++? Existing libraries on GNU radio?

Thank you very much in advance!

Cheers!

Maria


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